5 October 2022 in IEEE Journal of Solid-State Circuits
This article presents a fully dynamic 2–0 multistage noise-shaping (MASH) analog-to-digital converter (ADC) for low-power and high-precision applications. It implements the feedforward digitally with a 3-bit asynchronous successive-approximation-register (SAR) ADC and reuses it as the zeroth backend stage. Correlated level shifting (CLS) boosts the floating inverter amplifier (FIA) gain, embedded in the loop filter to implement integration. Dynamic body-biasing (DBB) technique helps boost the gain of a single-stage FIA with only one reservoir capacitor. Fabricated in 55-nm CMOS technology, the prototype ADC achieves measured SNDR of 94.0 and 96.9 dB dynamic range (DR) in 1-kHz BW at an oversampling ratio (OSR) of 125 while only consuming $2.87~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 179.4 dB and a DR-based FoM of 182.3 dB.
21 September 2022 in IEEE Journal of Solid-State Circuits
A 15-bit self-timed incremental analog-to-digital converter (ADC) for event-driven applications is presented. It is based on an asynchronous zoom ADC structure and a fully differential self-timed dynamic-amplifier (DA)-based integrator. Dynamic element matching (DEM) and chopping techniques mitigate the mismatch and noise. Measurements show that the ADC without oversampled clock achieves 93-dB SNR in a conversion time of 0.37 ms while consuming only 4.96- $\mu \text{A}$ current from a 1-V supply. This corresponds to a Schreier FoM of 177.3 dB. The 0.23-mm2 chip was fabricated in a standard 55-nm CMOS process.
10 January 2023 in IEEE Transactions on Circuits and Systems II: Express Briefs
This brief proposes a fully dynamic zoom ADC based on improved swing-enhanced floating-inverter amplifiers (SEFIAs) using the correlated-level-shifting (CLS) technique with $1250\times $ bandwidth/power scalability, by only changing the clock frequency. The improved SEFIA with CLS uses a reused capacitor to replace the dynamic biasing capacitor and input coupling capacitor, which simultaneously achieves both high gain and high output swing. Fabricated in a 55nm CMOS process, the prototype ADC with near-constant energy efficiency, which scales power from 453nW to $122~\mu \text{W}$ , achieves high resolution (> 95.2 dB) and high DR (> 96.7 dB) during the scalable bandwidth. At 5kHz BW, it achieves 97.3dB DR, 96.3dB SNDR, and 112.2dB SFDR, leading to FoMDR of 177.1dB and FoMSNDR of 176.1dB.