This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity. In the proposed scheme, the output voltage is coregulated by two loops, namely, the coarse loop and the fine loop. The coarse loop adopts a fast current-mirror flash analog to digital converter and supplies high output current to enhance the transient performance, while the fine loop delivers low output current and helps reduce the voltage ripples and improve the regulation accuracies. Besides, a digital controller is implemented to prevent contentions between the two loops. Fabricated in a 28-nm Samsung CMOS process, the proposed digital LDO achieves maximum load up to 200 mA when the input and the output voltages are 1.1 and 0.9 V, respectively, with a chip area of 0.021 mm². The measured output voltage drop of around 120 mV is observed for a load step of 180 mA.

A design-oriented analysis (DOA) method is presented, which lends sufficient insights into various Miller compensation schemes. The method predicts the nondominant poles of the Miller-compensated amplifiers in an intuitive manner, and it serves as a good supplement to the conventional analysis. The usage of DOA is verified by the various design examples given in this paper. Guided by DOA, a multistage amplifier capable of driving a large-capacitive load ($C_{L}$ ) with low power consumption is presented. This amplifier employs an active zero to extend its Miller loop bandwidth, thereby pushing the amplifier's nondominant poles to high frequencies and achieving larger gain bandwidth (GBW). Fabricated in a 0.18-$\mu \text{m}$ CMOS process, the amplifier achieves 1.18-MHz GBW and 59.6° phase margin when driving an 18-nF $C_{L}$ , while consuming 69.6 $\mu \text{W}$ from a 1.2-V supply. The design shows improved figures-of-merit compared with the prior state-of-the-art Miller-compensated multistage amplifiers.

This work presents a 48-1V dc–dc converter with an on-chip switch and gallium nitride (GaN) hybrid power conversion. By series connecting a 12-level Dickson switched-capacitor with a two-phase switched-inductor circuit, the capacitors take over most of the 48-V voltage stresses. The circuit, thus, reduces to an equivalent 4-1V converter, making the on-chip 5-V transistor applicable for a 48-V high-voltage design. Due to the easy integration of on-chip switches and superior switch figures of merit over other 48-1V counterparts, this proposed design is able to achieve the highest switching frequency, the lowest external switch count, and the improved power density compared with other prior-state-of-the-arts. The prototype was fabricated using a 0.18- $\mu \text{m}$ BCD process with an evaluation board volume of 17 mm $\times $ 15 mm $\times $ 2.6 mm. The converter achieves a maximum 8-A loading capacity with the input range from 36 to 60 V and the output from 0.5 to 1 V. The measured peak power efficiency is 90.2%, and the power density is 998 A/in ³ considering the power stage volume.

This article presents a fully dynamic scalable switched-capacitor delta-sigma modulator that achieves a 94.1-dB dynamic range (DR). Power-and- bandwidth scalability by only changing the clock frequency is achieved using a capacitively biased and swing-enhanced floating inverter operational transconductance amplifier (OTA). Fabricated in a 180-nm CMOS process, the prototype achieves an signal-to-noise-and-distortion ratio (SNDR) of >87 dB across 4x scaling from 100 to 400 kHz of the sampling frequency $f_{{S}}$ . At 200-kHz $f_{{S}}$ , it achieves an SNDR/DR of 89.3/94.1 dB while consuming 4 μW, leading to a DR-based Schreier figure of merit (FoM) of 177.1 dB.

This article presents a fully dynamic 2–0 multistage noise-shaping (MASH) analog-to-digital converter (ADC) for low-power and high-precision applications. It implements the feedforward digitally with a 3-bit asynchronous successive-approximation-register (SAR) ADC and reuses it as the zeroth backend stage. Correlated level shifting (CLS) boosts the floating inverter amplifier (FIA) gain, embedded in the loop filter to implement integration. Dynamic body-biasing (DBB) technique helps boost the gain of a single-stage FIA with only one reservoir capacitor. Fabricated in 55-nm CMOS technology, the prototype ADC achieves measured SNDR of 94.0 and 96.9 dB dynamic range (DR) in 1-kHz BW at an oversampling ratio (OSR) of 125 while only consuming $2.87~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 179.4 dB and a DR-based FoM of 182.3 dB.

In this paper, a fully integrated digitally assisted low-dropout regulator (LDO) for a NAND flash memory system is proposed and verified using 500 nm I/O CMOS transistors. By combining an amplifier (AMP)-based LDO with a comparator (CMP)-based LDO, the proposed LDO achieves both fast load response in the transient state and accurate regulation in the steady state, which are advantages of the CMP-based LDO and AMP-based LDO, respectively. Moreover, loop frequency stability is satisfied in a wide range of load currents between 0 and 150 mA by using the simple structure of the g _m -boost cell to insert an auxiliary path. For an input voltage range of 2.3-3 V and an output voltage of 2.1 V, the measured output droop is 225 mV for a 150 mA load step in the load transition time of 20 ns with the total bias current of 81 μA. The fabricated prototype chip occupies 160 × 610 μm ² with an on-chip output capacitor of 2 nF.