The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH₂F₂/CH₄/O₂/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO₂. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective Si1-x Ge x growth (0.35 ≤ × ≤ 0.40) with boron concentration of 1–3 × 1020 cm−3 was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance.

In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model. In the simulation, the minimum subthreshold swing (SS) reduced to 40 mV/decade with negligible hysteresis, and the on-current amplified by approximately three times. The N-DIBL effect was analyzed by building a model, and the results indicated that the N-DIBL is negatively correlated with the SS. Hence, it is indispensable to make trade-offs between the N-DIBL and SS in NC NWFET applications. Moreover, the Miller effect of a NCFET-based inverter was investigated for the first time. The Miller effect of the NC NWFET-based inverter was considerably improved owing to a high on-current and negative internal gate voltage (when external gate voltage is set to 0V), which is beneficial for high-speed circuit building based on NC NWFETs. The overshoot of the NC NWFET-based inverter is 43.1% less than that of the NWFET-based inverter, and the propagation delay of the NC NWFET-based inverter is 73.1% less than that of the NWFET-based inverter at ferroelectric thickness TFE=3nm.

The lateral and vertical gate-all-around (GAA) field-effect transistors are considered the most promising candidates for next generation logic device at and beyond 3-nm technology node. SiGe plays an important role in these devices as the sacrificial layer or channel material and needs isotropic etching. In this paper, an advanced etching process termed quasi atomic layer etching (qALE) is developed with advantages of controllable etch rate and atomically smooth surfaces. The qALE of SiGe is based on wet chemical etching, in which H ₂ O ₂ is applied to oxidate the surface with cyclic manner, and diluted buffered oxide etchant (dBOE) is applied to remove the oxide. The profiles of SiGe qALE for quasi-self-limited behavior, etch rate and the effect in concentration and temperature of H ₂ O ₂ have been studied. The etch per cycle (EPC) of Si _0.7 Ge _0.3 is 0.50 nm and the etching selectivity between Si _0.7 Ge _0.3 and heavily p-type doped silicon is 4.99 in Si/SiGe/Si stacked layers with (110) sidewall. The etch rate and the selectivity are influenced by Ge fraction of SiGe and the boron doping in Si. The root mean square (RMS) roughness after 60 cycles qALE is 0.183 nm indicating atomically smooth surfaces. Finally, the application of qALE for vertical nanowire compared with wet continuous etching is discussed in this work.