In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 10¹⁸ cm⁻³, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger I_ON/I_OFF ratio (3.15 × 10⁵) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

Complex nonlinear dependence of ultra-scaled transistor performance on its channel geometry and source/drain (S/D) doping profile bring obstacles in the advanced technology path-finding and optimization. A machine learning-based multi-objective optimization (MOO) workflow is proposed to optimize the sub-3-nm node gate-all-around (GAA) three-layer-stacked nanosheet transistors (NSFETs) accounting for the key performance knob of channel geometry and S/D doping profile. The artificial neural network (ANN) is trained to learn the compact current–voltage ( ${I}$ – ${V}$ ) relationship of NSFETs from 3-D technology computer-aided design (TCAD) simulation results. Based on the artificial neural network (ANN) model, MOO between threshold swing, on–off ratio, and ON-state current of NSFETs is performed with adaptive weighted sum theory. The proposed workflow efficiently suggests an optimized design window of channel geometry and doping profile of NSFETs. The proposed devices satisfy the 2025 International Roadmap for Devices and Systems (IRDSs) target in terms of electrical characteristics for digital circuits.

Complementary FET (CFET) is a promising candidate for CMOS scaling beyond 3-nm technology node. In this article, a novel hybrid channel CFET (HC-CFET) is proposed, which takes advantage of the vertical structure and simultaneously co-optimizes the preferred high-electron/hole-mobility surface of NMOS/PMOS on one substrate. The flexible combination of nanowires (NWs) and nanosheets (NSs) in the HC-CFET allows NMOS to have (100) channel surface orientation, while PMOS has (110) channel surface orientation without increasing the footprint of CFET pillars. Parasitic-aware device to circuit design-technology co-optimization (DTCO) analysis of the HC-CFET is performed based on advanced TCAD simulation of the device and comprehensive HSPICE simulation with TCAD-calibrated compact model. At the device level, the optimization of the channel surface orientation in the HC-CFET enables both NMOS and PMOS to obtain a current gain of more than 20%. By adjusting the wafer orientation and stacking type, HC-CFET exhibits higher frequency gain and comparable energy consumption in ring oscillator (RO) than multiscreen CFET (MS-CFET) and multibridge CFET (MB-CFET). After fully considering the impact of the stacking type on the static random access memory (SRAM) cell structure, (110) wafer together with n-NW on top of p-NS stack is the preferable approach to manufacture HC-CFET, which helps balance the speed, stability, and area of the SRAM cell.

Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by a series of parasitic parameters in these SRAM cells will diminish the scaling benefit introduced by new transistor architectures. In this article, we propose a universal methodology to determine the layout optimization direction of 6T static random-access memory (6T-SRAM) cells by studying the sensitivity of 6T-SRAM cell performance to various parasitic parameters. And adopt this method to optimize the CFET SRAM cell layout structure under the advanced nodes beyond 3 nm. The performances of CFET 6T-SRAM cells with different layout schemes are comparatively evaluated. It is found that the influence of the parasitic resistance on 6T-SRAM performances is double-sided, and parasitic resistances from transistor to power rail ( ${R}_{\mathrm {pds}}$ , ${R}_{\mathrm {pud}}$ ) and from access (AX) devices to bit-lines (BLs) ( ${R}_{\mathrm{bax}}$ ) have the most important effect on improving read noise margin (RNM) together with write margin (WM). The BL-first scheme with reduced ${R}_{\mathrm{bax}}$ and increased ${R}_{\mathrm {pud}}$ is proven to have 76.3% improvement in WM and 122.5% decrease in write time (WT) compared to the BL-last scheme, and a 63.8% improvement in RNM compared to conventional nanosheet architecture. Further optimized ${R}_{\mathrm{bax}}$ in the buried-BL scheme is proven to have higher WM, as well as lower WT. The BL-first scheme and buried-BL scheme is proven to be the most efficient approach to boost CFET SRAM performance.

In this article, one feasible fabrication approach for novel fishbone FETs using the channel-first and single work function metal (sWFM) processes is proposed and investigated by 3-D technical computer-aided design (TCAD) simulations. Through a small modification on the fabrication process of general gate-all-around (GAA) nanosheet FETs (NSFETs), the special fishbone-like channel composed of vertically stacked Si NSs and sandwiched SiGe nano-fins is experimentally demonstrated by the channel-first process. The simulated electrical characteristics show that the width of the nano-fins should be within 5 nm for a better gate control. Unlike traditional NSFETs, symmetrical threshold voltages ( ${V}_{\text {th}}\text{s}$ ) for n-type and p-type fishbone FETs can be achieved by using a sWFM, and $\Delta {V}_{\text {th}}$ is optimized by 99.26% compared with that of NSFETs. Meanwhile, it is also found that the SiGe nano-fins contribute more driving current for p-type devices. Therefore, the proposed fishbone FETs with sWFM not only exhibit significantly enhanced driving current but also provide good balance between the performances of n-type and p-type fishbone FETs with a little extra process cost.

Based on the bulk-Si substrate, the CMOS tree-like FETs including the FishboneFETs with bottom SiGe nano-fin and the TreeFETs without bottom SiGe nano-fin were both designed and experimentally fabricated. The growth of bottom SiGe layer with different Ge fraction following by an accurately selective etching is developed for realizing SiGe nano-fins between Si nanosheets (NSs). The results show that the I _on / I _off ratio (over 1×10 ⁵ ) and the short channel effects (SCEs) of TreeFETs are effectively optimized, and the effective channel width ( W _eff is increased for FishboneFETs on the same footprint. Due to the hole conduction advantage of SiGe nano-fin, the on-current ( I _on ) of p-type TreeFETs can be higher than that of n-type TreeFETs at V _OV =| V _gs - V _th |=0.5 V. Meanwhile, the surface scattering of SiGe nano-fin also affects the effective field-effect mobility. As the L _g scaling, both p-type tree-like FETs exhibit more obvious SCEs than n-type devices, which is maybe the reason of a lower hole barrier occurring by the valence band offset (Δ E _v ) obtained in the strained SiGe nano-fin. The results provided one meaningful guide for tree-like FETs optimizing future GAAFET process and CMOS circuits.