Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to three-dimensional (3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore’s law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs (CFET), 3D stack (3DS) FETs and vertical-channel transistors (VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

A new type of vertical nanowire (NW) /nanosheet (NS) field-effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that is compatible with processes used in the mainstream industry is proposed for the VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were used to fabricate pVSAFETs for the first time. Vertical GAA FETs with self-aligned high-k metal gates and a small effective-gate-length variation were obtained. Isotropic qALE, including Si-selective etching of SiGe, was developed to control the diameter/thickness of the NW/NS channels. NWs with a diameter of 10 nm and NSs with a thickness of 20 nm were successfully fabricated, and good device characteristics were obtained. Finally, the device performance was investigated and is discussed in this work.

High performance negative capacitance (NC) p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer are fabricated based on a conventional high-κ metal gate (HKMG) FinFETs fabrication flow. The devices show improved subthreshold swing (SS) values (34.5 mV/dec for 500-nm gate length (LG) and 53 mV/dec for 20-nm-LG devices) and slight hysteresis voltages (~9 mV for LG = 500 nm and ~40 mV for LG = 20 nm transistors). With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low interface state density (Dit) and the perfect channel electrostatic integrity.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 10¹⁸ cm⁻³, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger I_ON/I_OFF ratio (3.15 × 10⁵) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

We present a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1-xGex-channel gate-all-around (GAA) nanosheet field effect transistor (NSFET) for 5 nm node. The study encompasses physics-based quantum mechanical models both for P and NMOS with specified channel/wafer orientations and channel thicknesses, including (1) k.p model with Poisson solver for band structures, bandgap variations, and confined charge distributions, (2) Kubo-Greenwood model for low field mobility with considering surface roughness and stress, (3) Multi-subband Boltzmann transport equation (BTE) based on a state-of-the-art phase space approach is employed to evaluate device IV characteristics, (4) the threshold voltage (VT) variations with different channel/wafer orientations are also evaluated. Our simulation study shows that {110} wafer Ge channel can be an attractive option for 5nm node PMOS, and Si is still promising for NMOS due to strong quantum confinement in Ge channel.