In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 10¹⁸ cm⁻³, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger I_ON/I_OFF ratio (3.15 × 10⁵) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.

Complementary FET (CFET) is a promising candidate for CMOS scaling beyond 3-nm technology node. In this article, a novel hybrid channel CFET (HC-CFET) is proposed, which takes advantage of the vertical structure and simultaneously co-optimizes the preferred high-electron/hole-mobility surface of NMOS/PMOS on one substrate. The flexible combination of nanowires (NWs) and nanosheets (NSs) in the HC-CFET allows NMOS to have (100) channel surface orientation, while PMOS has (110) channel surface orientation without increasing the footprint of CFET pillars. Parasitic-aware device to circuit design-technology co-optimization (DTCO) analysis of the HC-CFET is performed based on advanced TCAD simulation of the device and comprehensive HSPICE simulation with TCAD-calibrated compact model. At the device level, the optimization of the channel surface orientation in the HC-CFET enables both NMOS and PMOS to obtain a current gain of more than 20%. By adjusting the wafer orientation and stacking type, HC-CFET exhibits higher frequency gain and comparable energy consumption in ring oscillator (RO) than multiscreen CFET (MS-CFET) and multibridge CFET (MB-CFET). After fully considering the impact of the stacking type on the static random access memory (SRAM) cell structure, (110) wafer together with n-NW on top of p-NS stack is the preferable approach to manufacture HC-CFET, which helps balance the speed, stability, and area of the SRAM cell.

In this article, one feasible fabrication approach for novel fishbone FETs using the channel-first and single work function metal (sWFM) processes is proposed and investigated by 3-D technical computer-aided design (TCAD) simulations. Through a small modification on the fabrication process of general gate-all-around (GAA) nanosheet FETs (NSFETs), the special fishbone-like channel composed of vertically stacked Si NSs and sandwiched SiGe nano-fins is experimentally demonstrated by the channel-first process. The simulated electrical characteristics show that the width of the nano-fins should be within 5 nm for a better gate control. Unlike traditional NSFETs, symmetrical threshold voltages ( ${V}_{\text {th}}\text{s}$ ) for n-type and p-type fishbone FETs can be achieved by using a sWFM, and $\Delta {V}_{\text {th}}$ is optimized by 99.26% compared with that of NSFETs. Meanwhile, it is also found that the SiGe nano-fins contribute more driving current for p-type devices. Therefore, the proposed fishbone FETs with sWFM not only exhibit significantly enhanced driving current but also provide good balance between the performances of n-type and p-type fishbone FETs with a little extra process cost.

A 16-nm-L_g p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

HfO₂-based ferroelectric materials have been widely studied for their application in ferroelectric FETs, which are compatible with conventional CMOS processes; however, problems with the material’s inherent fatigue properties have limited its potential for device application. This paper systematically investigates the effects of tensile stress and annealing temperature on the endurance and ferroelectric properties faced by Zr-doped HfO₂ ferroelectric film. The remnant polarization (P_r) shows an increasing trend with annealing temperature, while the change in the coercive electric field (E_c) is not obvious in terms of the relationship with tensile stress or annealing temperature. In addition, the application of tensile stress does help to improve the endurance characteristics by about two orders of magnitude for the ferroelectric material, and the endurance properties show a tendency to be negatively correlated with annealing temperature. Overall, although the effect of stress on the ferroelectricity of a HZO material is not obvious, it has a great influence on its endurance properties and can optimize the endurance of the material, and ferroelectricity exhibits a higher dependence on temperature. The optimization of the endurance properties of HZO materials by stress can facilitate their development and application in future integrated circuit technology.