Integrated three-port dc–dc converters (TPCs) exhibit obvious advantages in achieving flexible power flow regulation among photovoltaic (PV) module port, battery port, and load/grid port in distributed PV power generating systems. In the past three to five years, many new TPC schemes have been proposed, exhibiting unique characteristics, including isolation performance, number of components, and efficiency, which cannot be accurately described using traditional TPC classification methods. Moreover, there has been a lack of comparison of key performance indicators for a large number of TPC schemes in previous studies. Therefore, a comprehensive review on circuit topologies and control techniques of TPCs by properly defining key performance indicators becomes essential for converting high fluctuation solar energy into reliable and stable power while maintaining high efficiency and small footprint. This article is just to fill this gap by a comparative analysis and overview of classical and recently reported TPC schemes with key performance indexes. After introducing main operation modes of TPCs during one day, four topological structures of TPCs composed of two or three two-port dc–dc converters are classified and comparatively analyzed. Four important indexes of TPCs, namely voltage gain, control coupling, soft switching, and high-stress working, are used for a fair and comprehensive performance comparison. The advantages and disadvantages of various TPC schemes are featured, leading to a guidance for the selection of TPCs under different scenarios and valuable suggestions for the future development of TPCs.

Spiking neural networks (SNNs) have immense potential due to their utilization of synaptic plasticity and ability to take advantage of temporal correlation and low power consumption. The leaky integration and firing (LIF) model and spike-timing-dependent plasticity (STDP) are the fundamental components of SNNs. Here, a neural device is first demonstrated by zeolitic imidazolate frameworks (ZIFs) as an essential part of the synaptic transistor to simulate SNNs. Significantly, three kinds of typical functions between neurons, the memory function achieved through the hippocampus, synaptic weight regulation and membrane potential triggered by ion migration, are effectively described through short-term memory/long-term memory (STM/LTM), long-term depression/long-term potentiation (LTD/LTP) and LIF, respectively. Furthermore, the update rule of iteration weight in the backpropagation based on the time interval between presynaptic and postsynaptic pulses is extracted and fitted from the STDP. In addition, the postsynaptic currents of the channel directly connect to the very large scale integration (VLSI) implementation of the LIF mode that can convert high-frequency information into spare pulses based on the threshold of membrane potential. The leaky integrator block, firing/detector block and frequency adaptation block instantaneously release the accumulated voltage to form pulses. Finally, we recode the steady-state visual evoked potentials (SSVEPs) belonging to the electroencephalogram (EEG) with filter characteristics of LIF. SNNs deeply fused by synaptic transistors are designed to recognize the 40 different frequencies of EEG and improve accuracy to 95.1%. This work represents an advanced contribution to brain-like chips and promotes the systematization and diversification of artificial intelligence.

The complete replacement of silicon devices with silicon carbide (SiC) devices still faces many reliability challenges considering higher cost, higher junction temperature, and its wider variations. Hence, the junction temperature extraction for SiC devices becomes particularly significant recently. Furthermore, considering the latest emerging junction temperature extraction methods for SiC devices, it is critical to conduct a comprehensive review of these methods, including a scientific classification and systematical evaluation of these methods. This article is just to fill in this gap. First, a classification of these junction temperature methods for SiC devices will be conducted, including physical contact methods, optical methods, resistance–capacitance thermal network methods, and temperature-sensitive electrical parameter (TSEP) methods. Then, a comprehensive comparison of four-category methods for SiC devices have been conducted from different perspectives, such as the measurement accuracy, applicability, cost, online implementation, and power integration development. Moreover, considering the advantage of TSEP methods, this article has particulary compared and analyzed many newly proposed TSEP methods in recent years, which have been further divided into two subcategories based on their dependence on the load current. Their properties have also been evaluated for the first time in terms of the linearity, sensitivity, and other key features. This article analyzes many unresolved issues in the junction temperature extraction for SiC devices, among them, it is particularly worth emphasizing that innovative TSEP methods that consider the aging of SiC devices are still strongly demanding.

Novel normally-OFF AlGaN/GaN MIS-high electron mobility transistors (HEMTs) with a ZrO _x charge trapping layer are proposed. The deposition of the ZrO _x charge trapping layer on the partially recessed AlGaN in conjunction with the Al ₂ O ₃ gate dielectric has been accomplished. The developed MIS-HEMTs exhibit a threshold voltage of 1.55 ± 0.4 V and a maximum drain current of 730 ± 6 mA/mm, while associated low ON-resistance of 7.1 ± 0.2 Ω·mm, for a gate to drain separation of 3 μm. The TCAD simulation results are presented to explore the charge trapping and de-trapping behaviors. Moreover, the devices exhibit a high breakdown voltage. The results indicate the merits of employing ZrO _x charge trapping layer to realize the normally-OFF GaN devices with low ON-state resistance.

This article demonstrates the integrated comparators, hysteresis comparators, and sawtooth generators based on aluminum-gallium-nitride/gallium-nitride (AlGaN/GaN) metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). The integrated circuits (ICs) exhibit thermal stability from 25 °C to 250 °C in both static and transient performances. The threshold voltage ( V _th ) in depletion (D)-mode MIS-HEMT is modulated from -8.9 to -2.4 V to optimize the performance of integrated comparator circuits. The comparator can realize a large and stable comparison range of 3-9 V and a high voltage swing of 9.1 V, while the hysteresis comparator exhibits a good noise-immunity ability and stable hysteresis output. The sawtooth generator with the hysteresis comparator features a high amplitude (6.1 V) sawtooth signal at 500 kHz to realize a compact structure applicable to the high-voltage mixed-signal circuits. These results show the feasibility of MIS-HEMT monolithic comparator circuits in conversion systems.

Pulse test techniques are widely adopted in characterizing both the static and dynamic performances of semiconductor devices considering various device structures and operating conditions. For gallium nitride (GaN) devices, due to the current collapse phenomenon, fast and accurate measurement of their key electrical parameters, such as dynamic ON-state resistance ${R}_{\text {ds}, \mathrm{\scriptscriptstyle ON}}$ , switching rising time, fall time, switching losses, and short-circuit (SC) robustness, becomes essential. This article presents a comprehensive review of state-of-the-art pulse test setup methods such as the double-pulse test (DPT), multiple-pulse test (MPT), and SC test (SCT) for the first time, which facilitates the GaN device structure design and practical applications in high efficiency and power density power converters.