Novel normally-OFF AlGaN/GaN MIS-high electron mobility transistors (HEMTs) with a ZrO _x charge trapping layer are proposed. The deposition of the ZrO _x charge trapping layer on the partially recessed AlGaN in conjunction with the Al ₂ O ₃ gate dielectric has been accomplished. The developed MIS-HEMTs exhibit a threshold voltage of 1.55 ± 0.4 V and a maximum drain current of 730 ± 6 mA/mm, while associated low ON-resistance of 7.1 ± 0.2 Ω·mm, for a gate to drain separation of 3 μm. The TCAD simulation results are presented to explore the charge trapping and de-trapping behaviors. Moreover, the devices exhibit a high breakdown voltage. The results indicate the merits of employing ZrO _x charge trapping layer to realize the normally-OFF GaN devices with low ON-state resistance.

This article presents the enhancement-mode (E-mode) GaN p -channel heterojunction field-effect transistors ( p -FETs) with p -Al $_{\text{0.05}}$ Ga $_{\text{0.95}}$ N etching-target layer (ETL). The optimized high-selectivity etching technique achieves an etch rate of approximately 1 nm/min for p -GaN, while also generating a selectivity ratio of 4:1 between p -GaN and p -Al $_{\text{0.05}}$ Ga $_{\text{0.95}}$ N. High-yield E-mode p -FET with ETL has been obtained as the etching process window was expanded to 10 min. The devices achieved the characteristics of a threshold voltage ( $\textit{V}_{\text{th}}$ ) of $-$ 1.15 V and a maximum current density ( $\textit{I}_{\textit{D},\text{max}}$ ) of 6.16 mA/mm. Furthermore, the characteristics of multiple devices demonstrate the high consistency and reproducibility of p -FETs’ $\textit{V}_{\text{th}}$ and $\textit{I}_{\text{ON}}$ , thus providing significant opportunities for developing complementary circuit integration.

Devices under semi-on-state stress often suffer from more severe current collapse than when they are in the off-state, which causes an increase in dynamic on-resistance. Therefore, characterization of the trap states is necessary. In this study, temperature-dependent transient recovery current analysis determined a trap energy level of 0.08 eV under semi-on-state stress, implying that interface traps are responsible for current collapse. Multi-frequency capacitance–voltage (C-V) testing was performed on the MIS diode, calculating that interface trap density is in the range of $1.37\times {10}^{13}$ to $6.07\times {10}^{12}$${\mathrm{cm}}^{-2}$${\mathrm{eV}}^{-1}$ from $E_C-E_T=0.29$ eV to 0.45 eV.

In power conversion systems, the power devices often need to block high voltage levels during the OFF-state. The impact of such voltage stress can cause instability for the device. This article presents the investigation of the pulsed ${I}$ – ${V}$ (PIV) OFF-state drain stress test for the etch-free hydrogen plasma-treated p-GaN gate HEMT (H-treated devices). To quantitatively demonstrate the effect of the hydrogen plasma treatment process, the device with conventional p-GaN etching at the access region (etched devices) is monolithically fabricated. Remarkably, the hydrogen treatment could eliminate surface damage from the conventional etching process and provide passivation at the access region. The direct comparison of devices’ threshold voltage ( ${V} _{\text {TH}}$ ) shift and dynamic ON-resistance ( ${R} _{\text {on}}$ ) is obtained. Under a 200-V OFF-state drain stress, the H-treated device has a low ${V} _{\text {TH}}$ shift of 0.18 V, and the dynamic ${R} _{\text {on}}$ could also be efficiently suppressed by 24%. Meanwhile, the H-treated device has only a marginal 5% current reduction compared with 48% for the etched device at 200-V stress. An exploration of the origin of the superior device performances is carried out with the TCAD simulation, activation energy derivation, and capacitance measurement. For the H-treated device, the surface state improvement at the region and the reduction of the peak electric field at the gate edge become major reasons for the improved performance.

The dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with different passivation layers (SiSi3N4 or Si3N4/ZrO2 stack) under off-, semi-on, and ON-state stress have been investigated in this work. Under the OFF-state stress of 40 V, a 20% reduction in the maximum drain current has been observed in devices passivated with Si{3}N{4}, along with a degraded ${R}_{ \mathrm{\scriptscriptstyle ON}}$ that is 1.42 times higher than the initial ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . In contrast, devices passivated with Si3N4 or Si3N4/ZrO2 stack have only shown a 2% reduction, and the ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation is only 1.03 times higher than the initial ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . This can be attributed to the different interface states present in the two devices. According to the multifrequency $\vphantom {_{\int _{\text {a}}}}~{C}$ – ${V}$ curves, the Si3N4/GaN-cap interface trap density is in the range of $2\times 10^{{13}}$ – $5.5\times 10^{{13}}$ from ${E}_{C}-{0.47}$ to ${E}_{C}-{0.37}$ eV, and ZrO2/GaN-cap interface trap density is in the range of $2.7\times 10^{{12}}$ – $1.2\times 10^{{13}}$ from ${E}_{C}-{0.47}$ to ${E}_{C}-{0.31}$ eV. Under the semi-on state stress, the dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation exhibits a “bell-shaped” behavior in the Si3N4 or Si3N4/ZrO2 stack passivated sample. Arrenhius plots indicate that the sample passivated by Si3N4 has an activation energy of 0.06 eV, while the sample passivated by Si3N4 or Si3N4/ZrO2 stack has an activation energy of 0.16 eV, which means a deeper trap distribution. The ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation under semi-on/ ON-state stress in Si3N4 or Si3N4/ZrO2 passivated devices can be attributed to the hot-electron-related injection mechanism. Device designers must consider the trade-off between the high breakdown voltage (BV) and the ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation in Si3N4 or Si3N4/ZrO2 passivated devices.

This Letter presents tri-gate GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) with improved high-temperature performance for a monolithic integration platform, utilizing a low-damage digital recess technique. The fin structure followed by the multiple cycles of plasma oxidation and wet oxide removal process enables threshold voltage modulation from −9.1 V (D-mode) to +1.1 V (E-mode) in MIS-HEMTs, achieved by tuning the fin width between 800 and 56 nm on the same wafer. The E-mode device shows a low subthreshold swing of 76 mV/dec, a low on-resistance of 8.2 Ω·mm, and a low hysteresis of 26 mV. The E-mode device exhibits a small threshold voltage (Vth) shift of −0.13 V from room temperature up to 200 °C leading to logic inverters of stable characteristics with an inverter threshold voltage shift of only 0.16 V from 25 to 250 °C. These results validate the monolithic integration of tri-gate GaN to be promising for high-frequency and compact mixed-signal systems.