This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off.

This paper presents a broadband 3–3.7 GHz class-J Doherty power amplifier exploiting second harmonic tuning in the output network. Furthermore, the output impedance inverter is eliminated and its effect is embedded in the main device’s output matching network, thus trading off among bandwidth, efficiency, and gain. The proposed amplifier adopts two 10 W packaged GaN transistors, and it achieves in measurement 60–74%, and 46–50% drain efficiency at saturation and 6 dB output back-off, respectively, with a saturated output power of 43–44.2 dBm and a small-signal gain of 10–13 dB. The proposed DPA exhibits a simulated adjacent channel power ratio less than −30 dBc at 36 dBm average output power, when a 16-QAM modulation with 5 MHz bandwidth is applied to the 3.5 GHz carrier.

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for next generation computing systems. However, with increasing process variation and decreasing supply voltage, a big design challenge of embedded STT-MRAMs is to guarantee negligible read disturbance and high yield. To deal with the read reliability challenge, an offset compensated, high-speed sense amplifier (OCHS-SA) is proposed, which is based on combining the sensing circuit and latch sense amplifier (SA). The proposed OCHS-SA scheme offers four major advantages including offset compensation, high sensing margin (SM), strong positive feedback, and latching feature with compact area. Simulation results show that the SM is at least 700 mV at VDD = 1 V with a sensing time of 3.5 ns, and it provides the lowest energy consumption/area overhead over compared SAs.

In this brief, a novel low-power, low-area nonvolatile (NV) static random access memory (SRAM) that uses a single magnetic tunneling junction for store/restore operation is proposed. The proposed cell is dynamically reconfigurable in the background, which makes it a proper alternative to replace the SRAM cells of conventional field-programmable gate arrays (FPGAs) for the development of NV-FPGAs. The simulation results show that the proposed cell offers $8.8 {\times }$ lower store time, $1.52 {\times }$ ( $1.08 {\times }$ ) lower store-0 (store-1) energy, and $3.54 {\times }$ lower restore energy, in comparison with the recently reported work. In addition, a high loading speed of 1 ns is achieved by using a separately supplied initialization and pulsed overwrite schemes.

In this paper, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the drain of the common-source (CS) transistor. This new current path speeds up on-to-off transition of the CG transistor. In addition, the threshold voltage of the CG device is increased during on and off transitions which lowers the drain-source voltage of the CS device. Concurrently, these two phenomena minimize the power loss in both CS and CG transistors. To demonstrate the functionality of the FB technique, a cascode class-E PA is implemented in a 0.18-μm CMOS TSMC process at 1.8 GHz with 52% PAE and 27 dBm maximum output power.