Memcomputing is a novel non-Turing paradigm of computation that uses interacting memory cells (memprocessors for short) to store and process information on the same physical platform. It was recently proven mathematically that memcomputing machines have the same computational power of nondeterministic Turing machines. Therefore, they can solve NP-complete problems in polynomial time and, using the appropriate architecture, with resources that only grow polynomially with the input size. The reason for this computational power stems from properties inspired by the brain and shared by any universal memcomputing machine, in particular intrinsic parallelism and information overhead, namely, the capability of compressing information in the collective state of the memprocessor network. We show an experimental demonstration of an actual memcomputing architecture that solves the NP-complete version of the subset sum problem in only one step and is composed of a number of memprocessors that scales linearly with the size of the problem. We have fabricated this architecture using standard microelectronic technology so that it can be easily realized in any laboratory setting. Although the particular machine presented here is eventually limited by noise—and will thus require error-correcting codes to scale to an arbitrary number of memprocessors—it represents the first proof of concept of a machine capable of working with the collective state of interacting memory cells, unlike the present-day single-state machines built using the von Neumann architecture.

This paper presents the theoretical analysis of phase distortion (AM/PM) mechanisms in Gallium Nitride (GaN) Doherty power amplifiers (DPAs) and a novel approach to optimize the tradeoff between linearity and efficiency. In particular, it is demonstrated how it is possible to mitigate the AM/PM by designing a suitable mismatch at the input of the active devices, based on the identification of constant AM/PM and gain contour circles. The proposed theory is experimentally confirmed by source- and load-pull measurements and further validated through the design and realization of a 7 GHz 10W DPA based on GaN monolithic technology.

A theoretical validation of the offset lines method for design of Doherty power amplifiers is presented for the first time. The analysis is carried out considering the simplified unilateral active device model classically adopted in Doherty amplifier theory. In particular, it is proved that, in narrow band conditions, properly designed offset lines preserve the ideal load modulation across the full power sweep range. The demonstration is independent from the Doherty strategy adopted, e.g., in terms of output power back-off, even or uneven architecture. A simple analytical formula to calculate the proper length of the lines is given, and validated through a simulation example.

This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off.

Modern mobile communication signals require power amplifiers able to maintain very high efficiency in a wide range of output power levels, which is a major issue for classical power amplifier architectures. Following the load-modulation approach, efficiency enhancement is achieved by dynamically changing the amplifier load impedance as a function of the input power. In this paper, a review of the widely-adopted Doherty power amplifier and of the other load-modulation efficiency enhancement techniques is presented. The main theoretical aspects behind each method are introduced, and the most relevant practical implementations available in recent literature are reported and discussed.