This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off.

In this article, we propose a broadband fully integrated power amplifier (PA) using a waveform shaping harmonic matching network. A comprehensive theory is developed for the proposed multi-resonance harmonic matching network to derive design criteria for achieving wide bandwidth, low insertion loss, and optimum load impedances in the second- and third-harmonic frequency bands. Furthermore, it is shown that this network can be realized using a lower total inductance compared to a standard bandpass network which is an important feature in reducing chip area and fabrication cost. A fully integrated PA prototype is implemented using a 250-nm GaN-on-SiC process with 28-V supply. The PA provides 33.9–36.1dBm output power (at 2–3dB gain compression), 42–51% drain efficiency (DE), 38–48% power-added efficiency (PAE), and 10–12.2dB power gain, across 4.0–6.0GHz. The output-power 1-dB bandwidth is 3.6–5.6GHz (44.5%). For a 64-QAM signal with 8dB peak-to-average power ratio (PAPR) at 5.0GHz, the PA can provide 30.2dBm average output power and 32% average PAE with RMS error vector magnitude (EVM) of −34.0/−32.4/−28.4dB (2.0/2.4/3.8%) for 50/100/200MHz modulation bandwidth, without using digital predistortion (DPD). The maximum average output power and average PAE, under the linearity constraint EVM <−28dB, are respectively 32.1/32.0/30.2dBm and 39/38/32%, for modulation bandwidth of 50/100/200 MHz.

This paper presents a broadband 3–3.7 GHz class-J Doherty power amplifier exploiting second harmonic tuning in the output network. Furthermore, the output impedance inverter is eliminated and its effect is embedded in the main device’s output matching network, thus trading off among bandwidth, efficiency, and gain. The proposed amplifier adopts two 10 W packaged GaN transistors, and it achieves in measurement 60–74%, and 46–50% drain efficiency at saturation and 6 dB output back-off, respectively, with a saturated output power of 43–44.2 dBm and a small-signal gain of 10–13 dB. The proposed DPA exhibits a simulated adjacent channel power ratio less than −30 dBc at 36 dBm average output power, when a 16-QAM modulation with 5 MHz bandwidth is applied to the 3.5 GHz carrier.

This work presents the design and characterization of an ultralow-power core chip for electronically scanned arrays at X-band, implemented in 0.25-/0.5-μm E-/D-mode gallium arsenide (GaAs) pHEMT technology. In particular, design details are given about the two core functional blocks embedded in the microwave monolithic integrated circuit (MMIC): a 12-bit phase and amplitude control circuit and an 18-bit serial-to-parallel (S2P) interface. The S2P interface was designed resorting to a custom symmetric device model, expressly conceived for the time-domain simulations required for digital circuits. Due to the adoption of a differential structure with resistive pull-ups, it achieves a state-of-the-art power consumption of 2.2 mW/bit and nearly 87% yield. The analog circuit includes a 6-bit phase shifter (PS) and a 6-bit attenuator. To mitigate risks, two different PS architectures have been developed and are compared in this work, discussing advantages and drawbacks of the different solutions. Since the two designs share the same target specifications, a truly fair comparison can be made not only in terms of performance but also concerning robustness and repeatability, thus providing useful guidelines for the selection of the most appropriate strategy. In particular, it is shown that one architecture outperforms the other by about 2 dB and 1.5° in terms of insertion loss and rms phase error, respectively.

Growing deployment of more efficient communication systems serving electric power grids highlights the importance of designing more advanced intelligent electronic devices and communication-enabled measurement units. In this context, phasor measurement units (PMUs) are being widely deployed in power systems. A common block in almost all PMUs is a phase locked oscillator which uses a voltage controlled oscillator (VCO). In this paper, a triple frequency based voltage controlled oscillator is presented with low phase noise and robust start-up. The VCO consists of a detector, a comparator, and triple frequency. A VCO starts-up in class AB, then steadies oscillation in class C with low current oscillation. The frequency of the VCO, which is from 13.17 GHz to 16.03 GHz, shows that the frequency is tripling to 41.14–48.11 GHz. Therefore, its application is not limited to PMUs. This work has been simulated in a standard 0.18 µm CMOS process. The simulated VCO achieves a phase noise of −99.47 dBc/Hz at 1 MHz offset and −121.8 dBc/Hz at 10 MHz offset from the 48.11 GHz carrier.

Microwave core-chips are highly integrated MMICs that are in charge of all the beam-shaping functions of a transmit-receive module within a phased array system. Such chips include switches, amplifiers and attenuators, phase shifters, and possibly other elements, each to be controlled by external digital signals. Given the large number of control lines to be integrated in a core-chip, the embedding of a serial to parallel interface is indispensable. Digital design in compound semiconductor technology is still rather challenging due to the absence of complementary devices and the availability of a limited number of metallization layers. Moreover, in large arrays, high chip yield and repeatability are required. This paper discusses and compares challenges and solutions for the key sub-circuits of GaAs serial to parallel converters for core-chip applications, reviewing the pros and cons of the different implementations proposed in the literature.