A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.

A 16-nm-L_g p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

HfO₂-based ferroelectric materials have been widely studied for their application in ferroelectric FETs, which are compatible with conventional CMOS processes; however, problems with the material’s inherent fatigue properties have limited its potential for device application. This paper systematically investigates the effects of tensile stress and annealing temperature on the endurance and ferroelectric properties faced by Zr-doped HfO₂ ferroelectric film. The remnant polarization (P_r) shows an increasing trend with annealing temperature, while the change in the coercive electric field (E_c) is not obvious in terms of the relationship with tensile stress or annealing temperature. In addition, the application of tensile stress does help to improve the endurance characteristics by about two orders of magnitude for the ferroelectric material, and the endurance properties show a tendency to be negatively correlated with annealing temperature. Overall, although the effect of stress on the ferroelectricity of a HZO material is not obvious, it has a great influence on its endurance properties and can optimize the endurance of the material, and ferroelectricity exhibits a higher dependence on temperature. The optimization of the endurance properties of HZO materials by stress can facilitate their development and application in future integrated circuit technology.

In this article, a p-type high-k/metal gate (HKMG) FinFET with a special diamond-shaped channel on a bulk Si substrate for the formation of gate-induced quantum dot (QD) is reported. The electrical characteristics of the device at various temperatures and bias voltages for QD formation are extensively investigated. Remarkable oscillations in the drain current are observed for the 30-nm gate length (Lg) transistor at T =20 K. By analyzing the experimental results as well as the simulation data obtained by TCAD, it is found that the carriers are strongly localized at the small sharp tip of the channel and the thick spacers contribute to a large confinement potential for forming QD with a large charging energy of 30 meV. This provides a promising approach for large-scale QD fabrication and integration using the mainstream bulk complementary metal oxide semiconductor (CMOS) process.

Dual-comb ranging enables rapid, high-precision absolute distance measurements, but its performance is constrained by intrinsic phase noise, which induces temporal jitter and degrades pulse-to-pulse mutual coherence. Here, we propose a deep learning network Wavelet-Fused DenseNet (WFDNet) for hardware-free computational phase correction in dual-comb ranging. Through integration of complex wavelet decomposition and physics-guided feature encoding, the network, trained on model-generated data, can directly extract multi-scale time–frequency features to correct phase distortions and recover temporal coherence of the signals. Results from both simulated and experimental scenarios reveal that the approach can effectively suppress spectral noise and retrieve robust and unambiguous phases information, achieving high ranging accuracy with a standard deviation of 0.6 μm.