Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸$Ni$ and ²⁸$Si$, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs.

A 4-channel front-end electronics (4 × FEE) system for the muon drift tube in the ATLAS detector in the High-Luminosity LHC is presented. The overall channel architecture is optimized to reduce the power and area of the design. Each channel comprises a charge-sensitive preamplifier (CSP), shaper, discriminator and differential low-voltage signaling drivers. The proposed channel operates with a 5–100 fC input charge and exhibits a linear sensitivity of 8 mV/fC for the entire input charge range. The peaking time delay of the analog channel is 14.6 ns. At the output, the time representation of the input signal is provided in terms of the CMOS level and in scalable low-voltage signal (SLVS). The FEE consumes a current of 10.6 mA per channel from a single 1.2 V supply voltage. The full 4 × FEE design is realized in TSMC 65 nm CMOS technology and its die-area is 2 mm × 2 mm.

This paper presents the design and performance of a four-channel readout electronics system for the ATLAS muon chamber (MDT) to detect and measure charges resulting from proton-proton collisions. The design emphasizes speed, robustness, and efficiency in both area and power. Each channel comprises a charge-sensitive preamplifier (CSP), a shaper, a discriminator, and differential low-voltage signaling drivers. The analog channel exhibits a peaking time of 15 ns with a 60 pF detector capacitance and 4 ns without the detector capacitor. The circuit demonstrates linear sensitivity of 1 mV/fC at the CSP output and 8 mV/fC at the shaper output. Charge information in the range of 5–100 fC is extracted via time-over-threshold (ToT) decoding. Implemented in 65 nm CMOS technology, the design operates at a 1.2 V supply voltage.