In this letter, we demonstrate a novel PEALD-AlN/LPCVD-Si3N4 dual gate dielectric employed in enhancement-mode GaN MISFETs, where the gate recess is fabricated based on our proposed self-terminating gate recess etching technique using GaN cap layer as recess mask. By using LPCVD-Si3N4 and PEALD-AlN dual gate dielectric layer, the devices exhibit a high quality gate dielectric and a good GaN channel interface, yielding a high gate swing up to 18V and a high channel effective mobility of 137 cm2/V·s at such high gate bias. Thus, the fabricated devices feature a high maximum drain current density of 823 mA/mm, a threshold voltage of 2.6 V, an on-resistance of 7.4 Ω·mm, and an ON/OFF current ratio of 108 with gate-drain distance of 2 μm. Meanwhile, a high OFF-state breakdown voltage of 1290 V is achieved with 10 μm gate-drain distance. The corresponding specific on-resistance is as low as 1.76 mΩ·cm2, leading to a high Baliga’s figure of merit of 945 MW/cm2.

In this letter, we demonstrate a high-threshold-voltage and high-current-density normally-off SiN/AlN/ GaN-on-Si MIS-HEMT with in situ low-damage H ₂ /N ₂ plasma pretreatment. The in situ plasma pretreatment was performed in a plasma enhanced atomic layer deposition (PEALD) system prior to the PEALD-AlN deposition, which effectively suppress the interface trap densities between the AlN/GaN interface and increase the mobility of electrons to 198.80 cm $^{{2}}/\text {V} \cdot \text {s}$ . Therefore, the devices demonstrate state-of-art characteristics with a competitive maximum drain current of 683.75 mA/mm at ${V} _{\textit {GS}} =15\text{V}$ and a high threshold of 6.28 V. The devices also show ON/OFF current ratio of $10^{{8}}$ and off-state breakdown voltage of 1778 V.

AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMTs) with thick (>35 nm), high-κ (TiO₂/NiO), submicrometer-footprint (0.4 μm) gate dielectric are found to exhibit two orders of magnitude in lower gate leakage current (~1 nA/mm up to +3-V applied gate bias), higher IMAX (709 mA/mm), and higher drain breakdown voltage, compared to Schottky barrier (SB) HEMTs of the same geometry. The maximum extrinsic transconductance of both the MOSHEMTs and the SBHEMTs with 2 × 80-μm gate fingers is measured to be 149 mS/mm. The addition of the submicrometerfootprint gate oxide layer only results in a small reduction of the current gain cutoff frequency (21 versus 25 GHz, derived from S-parameter test data) because of the high permittivity (κ ≈ 100) of the gate dielectric. This high-performance submicrometer-footprint MOSHEMT is highly promising for microwave power amplifier applications in communication and radar systems.

An enhancement-mode (E-mode) p-type gallium nitride (p-GaN) gate high electron mobility transistor with a gate termination extension (GTE-HEMT) has been developed on a sapphire substrate, intended for power switching applications of kilovoltage (kV) level. The GTE-HEMT device exhibits a low ON-resistance ( R $_{\biosc{on}}$ ) of 19.3 $\Omega$ $\cdot$ mm, corresponding to a specific R $_{\biosc{on}}$ ( R $_{\biosc{on},\text{SP}}$ ) of 7.33 m $\Omega$ $\cdot$ cm $^{\text{2}}$ . Notably, the GTE-HEMT has achieved a breakthrough by increasing the breakdown voltage (BV) to 2573 V, surpassing the conventional p-GaN gate HEMT (Conv-HEMT) with its BV of 1679 V. The enhanced BV is ascribed to the gate termination extension (GTE) that reduces the gate-edge electric field peak, similar to a junction termination extension (JTE) in traditional Si power devices. In addition, the dynamic R $_{\biosc{on}}$ of the GTE-HEMT has been improved, with a normalized dynamic R $_{\biosc{on}}$ (dynamic R $_{\biosc{on}}$ /static R $_{\biosc{on}}$ ) of 1.4 and 2.6 for 650-and 1200-V OFF-state stress, respectively. The GTE-HEMT has been benchmarked to the state-of-the-art GaN power transistors, demonstrating its potential for high-voltage applications.

In this letter, we demonstrate a GaN-based E/D-mode (Enhancement/Depletion-mode) inverter with PEALD-AlN (Plasma Enhanced Atomic Layer Deposition) and LPCVD-SiN (Low Pressure Chemical Vapor Deposition) as bilayer gate dielectric, where the E-mode GaN-MISHEMT is fabricated based on our proposed self-terminating gate recess etching technique. The combination of the two dielectrics makes the device exhibits high gate swing and low dielectric/III-V interface state densities. So that the fabricated inverter shows a large logic swing, high temperature stability and low hysteresis effect.