In this article, the single event burnout (SEB) performances for 2DEG Al _x $\text{Ga}_{{1}-{x}}\text{N}$ channel p-GaN gate high electron mobility transistors (HEMTs) have been investigated comprehensively to reveal the failure mechanisms and broaden applications in harsh environments. As Al composition ${x}$ increases from 0.0 to 0.4, ${V}_{\text {BR}}$ increases from 500 to 730 V, and the corresponding SEB voltage ${V}_{\text {SEB}}$ at linear energy transfer (LET) = 10 pC/ $\mu \text{m}$ increases from 300 to 450 V. Possible mechanisms of Al _x $\text{Ga}_{{1}-{x}}\text{N}$ channel HEMTs from the perspective of electric field ( ${E}$ -field) are proposed. ${E}$ -field near source and drain side after radiation would have a high peak ${E}$ -field and that of p-GaN layer exceeds 3.3 MV/cm of critical ${E}$ -field for GaN material, causing SEB to occur (LET = 10 pC/ $\mu \text{m}$ ). When SEB occurs in HEMTs, ${E}$ -field would increase rapidly and cannot be recovered. A new phenomenon has been first discovered when SEB occurs in Al _x $\text{Ga}_{{1}-{x}}\text{N}$ channel HEMTs with p-GaN gate ( ${x} = {0.0}$ –0.4, step = 0.1). In addition to the back-channel effect, an excess of holes would be left in the buffer layer after electrons flow toward the drain. It allows the injection of an excess of holes in the buffer layer into the gate with low potential, resulting in a sharp increase in ${I}_{\text {G}}$ . Simulation results indicate that AlGaN channel HEMTs have great advantages in SEB performances compared with the traditional GaN channel HEMTs.

Soft errors induced by high energy particles have been a severe concern in integrated circuits. Especially in advanced nanoscale technology nodes, the phenomenon of multi-node-upset caused by charge sharing is becoming a crucial issue. However, this problem remains a challenge as there are only few mitigation methods. This study demonstrates a cost-efficient latch named CROUT featuring double-node-upset tolerance. Integrating coupled Schmitt-triggers and four always-on high-threshold transistors, CROUT is highly reliable in the presence of double-node-upset. To further validate this, a test chip was fabricated in the 28nm CMOS process and tested in a heavy-ion radiation environment. The experimental results indicated that the radiation tolerance is about 2x higher than the standard latches. Moreover, compared to other state-of-the-art multi-node-upset tolerant latches, its power-delay-product (PDP) is reduced by 6x. The results show that our proposed latch is highly reliable and cost-effective for the space application, which further can be made into a standard cell to be integrated into large-scale circuits.

In this article, we proposed a comprehensive model for predicting the degradation of SiC MOSFETs after gamma-ray irradiation. It is experimentally founded that SiC MOSFETs exhibit different degradation behaviors under gate bias (i.e., ${V}_{\text {GS}} =15$ V and ${V}_{\text {DS}} $ = 0 V) and drain bias (i.e., ${V}_{\text {GS}} $ = 0 V and ${V}_{\text {DS}} =400$ V) in terms of threshold voltage ( ${V}_{\text {TH}}$ ) and ON-resistance ( ${R}_{\text {ds}, \text{ON}}$ ). TCAD simulation shows that gate bias causes a high electric field in gate oxide above the MOS channel region, while drain bias generates relatively lower electric field in gate oxide around near-channel region. The differences in electric field under gate bias and drain bias lead to different hole yields and charge accumulation in gate oxide, which is the underlying physical mechanism for their different degradation behaviors. ${V}_{\text {TH}}$ is chosen as the parameter to quantify the accumulated charges in gate oxide and further predict irradiation-induced degradation. The relationship between the variation of threshold voltage ( ${\Delta} {V}_{\text {TH}}$ ) and the total ionizing doses (TIDs) under both gate and drain bias is formulated and validated. Comparison among measured data, TCAD simulation, and model prediction shows that the maximum prediction error is lower than 0.08 V, which proves the rationale and accuracy of the proposed degradation model. In addition, the two submodels for gate bias and drain bias are unified as one according to the time dependence effect (TDE) for TID irradiation. The proposed model could be useful to predict the degradation and/or lifetime of SiC MOSFETs in irradiation environments.

The breakdown voltage (BVDS) variation of 400V silicon-on-insulator (SOI) n-channel laterally diffused metal oxide semiconductor field effect transistors (NLDMOSFETs) is examined after exposure to total ionizing dose (TID). The results for OFF bias and ON bias are explored. For OFF bias, the BVDS increases first and then degrades with accumulated dose. For ON bias, the irradiated device shows soft breakdown after irradiation. The physical mechanisms for these variations are analyzed and confirmed by technology computer aided design (TCAD) simulation.

Spin–orbit torque magnetic tunnel junction (SOT-MTJ) is the memory cell of magnetic random access memory (MRAM), which is a promising candidate for upper level cache in the harsh environment due to nonvolatility, high speed, and high endurance. Therefore, it is significant to research the mechanism of irradiation effects on the SOT-MTJ before its integration onboard. This article investigates the ionization and displacement damage of in-plane magnetic anisotropy SOT-MTJ, including 1-MeV electron and 17.2-keV He ⁺ and ⁶⁰ Co gamma irradiations with various fluences and doses, respectively. The devices are resilient to tunnel magnetoresistance (TMR), whereas the magnetic properties are changed after irradiation. The 100-Mrad (Si) gamma and 17.2-keV He ⁺ irradiations generate similar damages on the device performances, in the aspects of the magnetic anisotropy and critical current density ( $J_{\mathrm {c}}$ ). However, the displacement damage originating from the electron irradiation does not have a significant influence on $J_{\mathrm {c}}$ . In addition, the saturation magnetization and exchange bias field are changed by irradiations without regularity. Some possible mechanisms are discussed to explain the experimental results through the simulation of stopping and range of ions in matter (SRIM) and microstructural tests.

Recently, Shu et al. published “Numerical and Experimental Investigation of TID Radiation Effect on the Breakdown Voltage of 400 V SOI NLDMOS.” This short article is an extension of that earlier article. The breakdown voltage of 400-V silicon-on-insulator n-channel laterally diffused metal-oxide semiconductor field-effect transistors with different drift region lengths are examined after exposure to total ionizing dose. The variation observed is analyzed using technology computer-aided design simulation.