This work presents highly responsive gate-controlled p-GaN/AlGaN/GaN ultraviolet photodetectors (UVPDs) on Si substrates with a high-transmittance ITO gate. The two-dimensional electron gas (2DEG) in the quantum well of the polarized AlGaN/GaN heterojunction was efficiently depleted by the p-GaN gate, leading to a high photo-to-dark current ratio (PDCR) of 3.2 × 10⁵. The quantum wells of the p-GaN/AlGaN and AlGaN/GaN heterojunctions can trap the holes and electrons excited by the UV illumination, thus efficiently triggering a photovoltaic effect and photoconductive effect, separately. Furthermore, the prepared photodetectors allow flexible adjustment of the static bias point, making it adaptable to different environments. Compared to traditional thin-film semi-transparent Ni/Au gates, indium tin oxide (ITO) exhibits higher transmittance. Under 355 nm illumination, the photodetector exhibited a super-high responsivity exceeding 3.5 × 10⁴ A/W, and it could even exceed 10⁶ A/W under 300 nm illumination. The well-designed UVPD combines both the advantages of the high-transmittance ITO gate and the structure of the commercialized p-GaN/AlGaN/GaN high-electron-mobility transistors (HEMTs), which opens a new possibility of fabricating large-scale, low-cost, and high-performance UVPDs in the future.

To enhance gate swing and reduce gate leakage in p-GaN gate high electron mobility transistors (HEMTs), this work introduces novel metal–insulator–semiconductor (MIS) p-GaN tunneling gate HEMTs with an ultrathin Al₂O₃ tunneling layer. By varying the oxygen sources of atomic layer deposition (ALD), as well as the Al₂O₃ thickness of the MIS structure, we demonstrate the following results: 1) overdose hydrogen introduced by Al₂O₃ deposition using H₂O as oxygen source severely deactivates the Mg dopants, negatively shifts the threshold voltage $\textit{V}_{\text{TH}}$, and undermines the dynamic performance; 2) the MIS structure can effectively boost the forward bias gate breakdown voltage $\textit{V}_{\text{G-BD}}$; 3) thick Al₂O₃ insulator of the MIS structure can, however, undermine the dynamic stability; and 4) MIS p-GaN tunneling gate HEMTs, with a 3-nm ultrathin Al₂O₃ insulator deposited using O₃ as the oxygen source, exhibit an improved $\textit{V}_{\text{G-BD}}$ from 12 to 13.2 V, a suppressed gate leakage, an optimized $\textit{V}_{\text{TH}}$ from 1.8 to 2.2 V, and unaffected $\textit{V}_{\text{TH}}$ stability and dynamic $\textit{R}_{\text{on}}$ performances. This work not only exposes the drawbacks of the traditional MIS p-GaN gate HEMTs but also proposes a novel MIS p-GaN tunneling gate structure to dedicatedly balance the static and dynamic performance, thus providing a new option for fabricating high-reliability HEMTs.

Mg out-diffusion during epitaxial growth in MOCVD chambers poses significant challenges in simultaneously achieving a decent threshold voltage ${V}_{\text {TH}}$ and on-resistance ${R}_{\text {ON}}$ . In this work, by inserting a GaN layer with thickness ${t}_{\text {GaN}}$ of 0/5/10 nm between the p-GaN cap and the AlGaN barrier to tune the Mg profile, we found that: 1) the forward gate leakage current of p-GaN gate high-electron-mobility transistors (HEMTs) was independent of ${t}_{\text {GaN}}$ ; 2) excessive Mg diffusion into the barrier and channel layer of the HEMTs without this GaN insertion layer severely jeopardized stability; 3) HEMTs with ${t}_{\text {GaN}}$ of 5-nm achieved balanced ${V}_{\text {TH}}$ of 2.25 V, ${R}_{\text {ON}}$ of $9.04~\Omega \cdot $ mm, and off-state leakage current as low as $10^{-{8}}$ A/mm at 650 V; and 4) Mg doping engineering successfully kept the dynamic ${R}_{\text {ON}}$ degradation within $1.2\times $ under high-voltage off-state stress and ${V}_{\text {TH}}$ shift by 0.1 V under bias-temperature instability (BTI) stress. These results indicate that dedicated tailoring of the Mg doping profile in the p-GaN layer can achieve high ${V}_{\text {TH}}$ and low ${R}_{\text {ON}}$ simultaneously, offering a practical approach to enhance the performance and reliability of p-GaN gate HEMTs.

The explosive demand for high-performance secondary power sources in artificial intelligence (AI) has brought significant opportunities for low-voltage GaN devices. This paper focuses on research on high-efficiency and high-reliability low-voltage p-GaN gate HEMTs with a gate–drain distance, L_GD, of 1 to 3 μm in our pilot line, manufactured on 6-inch Si using a CMOS-compatible process, with extraordinary wafer-level uniformity. Specifically, these fabricated p-GaN gate HEMTs with an L_GD of 1.5 μm demonstrate a blocking voltage of over 180 V and a high V_TH of 1.6 V and exhibit a low R_ON of 2.8 Ω·mm. It is found that device structure optimization can significantly enhance device reliability. That is, through the dedicated optimization of source field plate structure and interlayer dielectric (ILD) thickness, the dynamic ON-resistance, R_ON, degradation of devices with an L_GD of 1.5 µm was successfully suppressed from 60% to 20%, and the V_TH shift was significantly reduced from 1.1 to 0.5 V. Further, the devices also passed preliminary gate bias stress and high-voltage OFF-state stress tests, providing guidance for preparing high-performance, low-voltage p-GaN gate HEMTs in the future.

The channel temperature distribution and breakdown points are difficult to monitor for the traditional p-GaN gate HEMTs under high power stress, because the metal gate blocks the light. To solve this problem, we processed p-GaN gate HEMTs with transparent indium tin oxide (ITO) as the gate terminal and successfully captured the information mentioned above, utilizing ultraviolet reflectivity thermal imaging equipment. The fabricated ITO-gated HEMTs exhibited a saturation drain current of 276 mA/mm and an on-resistance of 16.6 Ω·mm. During the test, the heat was found to concentrate in the vicinity of the gate field in the access area, under the stress of V_GS = 6 V and V_DS = 10/20/30 V. After 691 s high power stress, the device failed, and a hot spot appeared on the p-GaN. After failure, luminescence was observed on the sidewall of the p-GaN while positively biasing the gate, revealing the side wall is the weakest spot under high power stress. The findings of this study provide a powerful tool for reliability analysis and also point to a way for improving the reliability of the p-GaN gate HEMTs in the future.