A high-efficiency three-dimensionally (3-D) shaped polymer multi-jet impingement cooler based on cost-efficient fabrication techniques is introduced for the cooling of high-power applications. State-of-the-art highly efficient multi-jet cooling solutions rely on expensive Si or ceramic fabrication techniques, while low-cost cooling solutions have been proposed for less performant single-jet impingement. In this paper, we present the concept, modeling, design, fabrication, experimental characterization, and benchmarking with literature data of a multi-jet impingement based liquid cooling solution, fabricated using low-cost polymer fabrication techniques, targeted to directly cool the backside of high-power devices. For the modeling study, unit cell model and full system level models are used to study the nozzle array scaling trends and thermal and fluidic jet-to-jet interactions. Furthermore, design guidelines for high-power electronics cooling are provided, including geometry selections, material selection, and fabrication techniques. Based on the design guidelines and cooling concept, this paper demonstrates a 3-D-shaped polymer impingement cooler with a 4 × 4 nozzle array, showing a very good thermal performance with low required pumping power. The multi-jet cooler can achieve heat transfer coefficients up to 6.25 × 10 ⁴ W/m ² ·K with a pump power as low as 0.3 W. The benchmarking study confirms furthermore that multi-jet cooling is more efficient than single-jet cooling and that direct cooling on the backside of the semiconductor device is more efficient than cooling the substrate or base plate.

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This Tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

Ring modulators for silicon photonic (SiPho) optical transceivers are extremely thermally sensitive and require thermal tuning for stable operation. This tuning is achieved with integrated heaters and in this work two aspects of the heaters are investigated: firstly, how to thermally model the heater-waveguide system in a SiPho ring modulator. Secondly, how to improve the energy efficiency by adapting the design in order to minimize the thermal tuning power consumed by the heater. Silicon substrate undercut (UCUT) is done in order to achieve out-of-plane thermal isolation and prevent heat flow directly into the Si substrate below the device. Introducing the UCUT increases the heater efficiency ($\eta _{h}$) with a factor X3.08. It is shown that the influence of the UCUT cross section on the heater efficiency can be neglected, only the total area and metals significantly influence the thermal behaviour. Comparison between electro-thermal and pure thermal simulation shows very similar behaviour. Finally, the UCUT causes an increase in thermal time constant with factor X3.68.

The electromigration (EM) activation energy (EA) of alternative metals, such as Ru and Co, was obtained using low-frequency noise (LFN) measurements. High activation energies were expected, but values of ≈1 eV are found, most likely related to diffusion along with the metal-dielectric interface. Wafer-level accelerated EM tests were carried out to compare the LFN EA to the EM EA in the Ru wires. The calculation of the EM EA is found to be strongly dependent on the assumed temperature profile in the wire due to Joule heating (JH). The temperature profile was calculated analytically, assuming the contacts are at ambient temperature. For a void forming in direct proximity of the contact, the EM EA then matches the LFN EA. For a void at average wire temperature (ambient + JH), EA≈ 2 eV. In addition to demonstrating the application of LFN to study EM in alternative metals, this article also cautions for the impact of JH on the calculation of EA in interconnects.

This article presents the design, fabrication, experimental characterization, and modeling analysis of the chip-level hotspot targeted liquid impingement jet cooling for high-power electronics. The hotspot targeted jet impingement cooling concept is successfully demonstrated with a chip-level jet impingement cooler with a 1-mm nozzle pitch and 300-μm nozzle diameter fabricated using high-resolution stereolithography (additive manufacturing). The computational fluid dynamics (CFD) modeling and experimental analysis show that the improved hotspot targeted cooler design with fully open outlets can reduce the on-chip temperature difference by 70% compared with the full array cooler at the same pumping power of 0.03 W. The local heat transfer coefficient can achieve 15 × 10 ⁴ W/m ² K with a local flow rate per nozzle of 40 mL/min, requiring a pump power of 0.6 W. The benchmarking study proves that the hotspot targeted cooling is much more energy-efficient than uniform array cooling, with lower temperature difference and lower pump power.

A new thermal model based on a distributed and fast modeling approach for the modeling of gallium nitride (GaN) power devices is presented in this paper. The model is based on the application of Green's function theory to obtain an analytical solution of the heat conduction equation. The model comprises an accurate, spatially distributed, and fast algorithm that calculates a 2-D thermal response at the 2-D electron gas level of GaN power devices in the steady-state and the transient regime. In comparison with finite element method finite-element model simulations, the model achieves a significant reduction of the computational time while retaining very good accuracy. The model shows strong capabilities for thermal analysis with respect to parameters that have a significant impact on the thermal behavior. Moreover, the nonlinear effect associated with the temperature-dependent thermal conductivity is encompassed together with the impact of package and ambience. As a validation study, the thermal behavior of packaged GaN devices is experimentally characterized by means of infrared thermography. An excellent agreement between the model results and experiments is observed.