The unprecedented high-speed switching of Wide Bandgap (WBG) power devices may change the partial discharge (PD) behaviors of power modules, busbars and loads. However, very little research has been published on PD behaviors under square-wave pulses with ultra-fast dv/dt. To address this problem, this paper studies PD behaviors of direct bonded copper (DBC) samples with different trench distances and chamfer radii under single and repetitive square pulses with ultra-fast dv/dt. The results show that for the single pulse excitation partial discharge inception voltage (PDIV) decreases with increasing rise time if the pulse width is shorter than 300 s, and PDIV decreases with increasing pulse width. For repetitive pulse excitation, PDIV increases linearly with trench distance if the chamfer radius is larger than 0.5 mm, while it follows a concave curve if the chamfer radius is less than 0.5 mm. On the other hand, for a fixed trench distance, the PDIV changes quadratically with the chamfer radius increasing from 0 mm (right angle) to 0.7 mm. Based on experimental results, a PD model with bubble expansion theory is to explain the PD mechanism under ultra-fast dv/dt excitation, and an empirical equation for PDIV prediction is also derived.

Medium-voltage (e.g., 10 kV rated) silicon carbide (SiC) devices have great potentials in medium-voltage variable speed drives. But their high switching dv/dt can increase the voltage stress on motor windings and cause partial discharges. This paper presents a partial discharge study of a medium-voltage form-wound winding under two-level square-wave voltage pulses. A 10 kV SiC device-based test platform is built to generate voltage pulses with high dv/dt. A three-step test approach is proposed and employed to systematically investigate the effects of various voltage parameters on partial discharges. These include voltage rise/fall time, voltage pulse width, pulse repetitive rate, duty ratio, voltage polarity, fundamental frequency, and modulation index. Partial discharge inception voltages (PDIVs) and repetitive partial discharge inception voltages (RPDIVs) of the sample are measured with varied voltage parameters. Test results show that voltage rise/fall time is a major affecting factor which reduces PDIVs of the winding sample by 6.5% when it decreases from 800 ns to 100 ns. Based on test results, a hypothetical partial discharge mechanism is presented to explain the effects of fast voltage rise/fall edges. An empirical equation is also derived to estimate PDIVs of a winding sample under various voltage rise/fall time and pulse width conditions.

Partial discharge (PD) is a major cause of degradation of motor winding insulation. It is a challenge to the successful electrification of all types of ground, sea, and aerial vehicles. However, the mechanism of PD under pulsewidth modulated voltages is not fully understood. This article studies PD inception characteristics in twisted pairs under single voltage pulses with reduced voltage overshoot, aiming to study the PD inception characteristics and mechanism without the influences of memory effects and voltage overshoot. The tests are conducted with a lab-designed 10-kV silicon carbide (SiC) device-based voltage pulse generator. The generator can produce voltage pulses with variable rise/fall times and pulse widths to emulate the output voltages of both silicon (Si) and SiC device-based power electronics converters. The voltage overshoot in this study has been limited to less than 5%. In addition, single voltage pulses are utilized as the excitation to remove charge memory effects. PD inception voltages, PD current magnitudes, and PD time delays of twisted pair samples are measured under various test conditions. It is found that the partial discharge inception voltage (PDIV) of the test sample decreases with reduced voltage rise time and increased voltage pulsewidth. Based on the test results, the impacts of voltage rise/fall times and pulse widths on PD behavior are explained using the extended volume-time theory. The relationships between PDIV, voltage rise/fall time, and pulsewidth are presented through empirical equations. Test results and analysis provide insights on the impacts of emerging wide bandgap devices in applications on motor winding insulations.

This article presents the short-circuit (SC) capability evaluation of TO-247-3 packaged silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) based on tests under different drain biases and gate biases. Compared with the 900-V Si super-junction MOSFET and the 1200-V Si trench-gate field-stop insulated gate bipolar transistor (IGBT), SiC devices show higher saturation current per die area, which requires more rigorous chip design consideration to reach an acceptable SC withstand time (SCWT). The test results also reveal that the SC withstand capability of SiC MOSFETs can still be enhanced. Thus, in both chip design and detection circuits, several novel approaches investigated in recent years, which could potentially improve SC ruggedness of SiC device-based systems, are discussed at the end of this article.

This paper presents a self-sustained circuit building block (CBB) that utilizes 10-kV silicon carbide (SiC) devices as the main switches. The CBB achieves a self-sustained operation by powering the gate drives of its main switches with the energy from its dc bus capacitor. The CBB can serve as one of the sub-modules in a multilevel converter for high-voltage applications. This paper focuses on the design of the 10-kV SiC device’s gate drive and its associated auxiliary power supply (APS). The gate drive and its APS are the major technical challenges in the CBB development. The gate drive in the CBB features a common mode transient immunity (CMTI) over 200 kV/ls and fast protection functions. Its APS is based on an active voltage divider concept and achieves 7-kV input voltage with simple circuit structure and control scheme. The operational principles and design guidelines of the gate drive and its APS are presented in detail. Test results of the CBB in a double-pulse test setup with a 7-kV dc bus voltage are presented to validate the design. Reliable operation of the CBB is demonstrated under dv/dt up to 100 kV/ls.