Ferroelectric vertical gate-all-around field-effect-transistor (Fe-VGAAFET) suits a memory cell with a 5 nm technology node and beyond since it is less constrained by gate length, thereby providing sufficient space for the ferroelectric film compared with ferroelectric FinFET (Fe-FinFET) and ferroelectric lateral gate-all-around field-effect-transistors (Fe-LGAAFET). Also, Fe-VGAAFET achieves multilayer vertical stacking, which further increases the integrated density of devices. Here, we develop ferroelectric vertical sandwich gate-all-around field-effect-transistors (Fe-VSAFETs) with large memory windows (the maximum 2.3 V), high program/erase speeds (100 ns), and excellent retention properties using a self-aligned high- $\kappa $ metal gate process. Furthermore, vertical nanosheet devices with two channel thicknesses of approximately 16 and 42 nm and nanowire devices with a channel diameter of 30 nm were successfully fabricated, and excellent device characteristics were obtained.

In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model. In the simulation, the minimum subthreshold swing (SS) reduced to 40 mV/decade with negligible hysteresis, and the on-current amplified by approximately three times. The N-DIBL effect was analyzed by building a model, and the results indicated that the N-DIBL is negatively correlated with the SS. Hence, it is indispensable to make trade-offs between the N-DIBL and SS in NC NWFET applications. Moreover, the Miller effect of a NCFET-based inverter was investigated for the first time. The Miller effect of the NC NWFET-based inverter was considerably improved owing to a high on-current and negative internal gate voltage (when external gate voltage is set to 0V), which is beneficial for high-speed circuit building based on NC NWFETs. The overshoot of the NC NWFET-based inverter is 43.1% less than that of the NWFET-based inverter, and the propagation delay of the NC NWFET-based inverter is 73.1% less than that of the NWFET-based inverter at ferroelectric thickness TFE=3nm.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

This paper investigates the effect of total ionizing dose radiation on back-gate interface traps in SOI NMOSFETs. The concentration and energy distribution of interface traps at Si/SiO ₂ back-gate interface of SOI NMOSFETs during irradiation are studied by the direct-current current-voltage technique. When transistors are subjected to radiation, DCIV bulk current increases. The calculated results suggest that the interface trap density increases and its equivalent energy level is far away from the midgap with irradiation dose increasing, which can be explained by the energy distribution of interface traps. The interface trap energy density $D_{IT}(E_{IT})$ as a function of the energy level $E_{IT}$ has been obtained by the least square optimization and shows the typical “U-shape” distribution. In detail, the rising humps at equivalent energy level in $D_{IT}(E_{IT})$ curves are due to Si-H bonds that are broken down after irradiation, which corresponds to the increasing trap density. Moreover, it is found that the energy level of interface traps is redistributed after irradiation. The peak of humps in $D_{IT}(E_{IT})$ curves occurs at the farther energy level with the increase of dose, which is similar to the equivalent energy level. It might arise from the shallow energy level of interface traps induced by radiation.

For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge_0.8Si_0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge_0.8Si_0.2-selective etching of Ge and crystal-orientation selectivity of Ge oxidation, has been developed to control the etch rate and the size of the Ge nanowires. The ALE of Ge in p⁺-Ge_0.8Si_0.2/Ge stacks with 70% HNO₃ as oxidizer and deionized (DI) water as oxide-removal was investigated in detail. The saturated relative etched amount per cycle (REPC) and selectivity at different HNO₃ temperatures between Ge and p⁺-Ge_0.8Si_0.2 were obtained. In p⁺-Ge_0.8Si_0.2/Ge stacks with (110) sidewalls, the REPC of Ge was 3.1 nm and the saturated etching selectivity was 6.5 at HNO₃ temperature of 20 °C. The etch rate and the selectivity were affected by HNO₃ temperatures. As the HNO₃ temperature decreased to 10 °C, the REPC of Ge was decreased to 2 nm and the selectivity remained at about 7.4. Finally, the application of ALE in the formation of Ge nanowires in vGAAFETs was demonstrated where the preliminary I_d–V_ds output characteristic curves of Ge vGAAFET were provided.

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si_0.2Ge_0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si_0.2Ge_0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si_0.2Ge_0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si_0.2Ge_0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO₃ and H₂O₂ solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H₂O₂ solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.