In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of ON-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver ~4 A at 2 V and show a median leakage of 1.3 μA at 25 °C and 3.8 μA at 150 °C measured at a reverse voltage of -200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing (LAC) and the length of field plate. We observed a saturated BV of ~600 V for the GET-SBDs with LAC larger than 5 μm. The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 μm-thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 μm) and remains at a value of ~10 nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature.

In this paper a measurement methodology, using a two-dimensional electron gas (2DEG) resistor, is used to evaluate the dispersion of three different type of buffers, namely a step graded buffer, a buffer with low temperature (LT) AlN interlayers and a superlattice buffer. Together with a dedicated Design of Experiments (DOE), these measurements allowed us to identify the physical origin of the dispersion and identify the key parts of the buffer which influence the buffer-induced dispersion of the 2DEG.

In this letter, the dynamic R _on degradation mechanisms of the p-GaN gate HEMTs induced by off-state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including V _TH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The V _TH positive shift diminishes the drain current by shrinking the overdrive V _GS , which however, can be compensated by a higher V _GS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and V _TH shift have a very slow recovery process.

Substrate ramps and stepped stress transient measurements are applied to study vertical charge transport mechanisms in GaN-on-Si power HEMTs. By choosing appropriate bias points for substrate stress it is possible to single out the dominant charge transport mechanism: at low negative biases transport through carbon-doped GaN manifests itself in negative (decreasing) current transients with apparent activation energy (E _A ) = 0.29 eV, while at larger negative voltages transport through unintentionally doped GaN is characterized by positive (increasing) current transients (E _A = 0.38 eV). We present experimental evidence for 3D variable range hopping taking place in C-doped GaN and 1D hopping along the dislocations in unintentionally doped GaN. By investigating transients obtained from bidirectional voltage steps of 10 V potential difference in the range 0 to -140 V, we observe that hopping transport through dislocations shows non-Ohmic behavior at low substrate biases, which manifests itself in a time constant τ strongly dependent on bias. We propose that this can be explained by the existence of a diode junction between the dislocation core and the 2D electron gas (2DEG).

A sufficiently low transmission loss in radio frequency (RF) is one of the critical requirements for GaN-on-Si RF devices to achieve high performance. We have systematically studied the mechanism and effect of the AlN nucleation layer on the RF loss of the GaN-on-Si device buffer stack. Our results show that the RF loss is strongly influenced by the growth parameters of the AlN nucleation layer during epitaxial process. It is observed that the AlN nucleation layer grown at a low thermal budget with a low density of deep surface pits can efficiently reduce the AlN/Si interface loss by suppressing the conductive channel at AlN/Si interface which is governed largely by the thermal diffusion of Al and Ga into the Si substrate. By optimizing the growth process of the AlN nucleation layer, the RF loss of the GaN-on-Si device buffer can be dramatically reduced by up to ∼40%.

GaN power ICs on engineered substrates of Qromis substrate technology (QST) are promising for future power applications, thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bears a breakdown voltage of > 650 V under the leakage criterion of 10 μA/mm2 at 150 ∘C. The fabricated 36 mm power HEMTs with LGD of 16 μm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 μA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.