This paper presents a low-noise inverter-based current-mode instrumentation amplifier with tunable gain and bandwidth for electromyogram (EMG) and electrooculogram (EOG) biopotential signals, targeting low input noise while maintaining low power consumption. The gain tuning method is based on pseudo-resistors, whereas the bandwidth is tunable due to a varactor system that is controlled by the same control voltage that tunes the gain. The circuit was designed and manufactured using the 110 nm UMC CMOS technology node, occupying an area of 0.624 mm². The circuit presents a functioning mode for each biopotential signal with different characteristics, for the EMG a gain of 34.7 dB and a bandwidth of 1412 Hz was measured, with an input referred noise of 1.407 μV which matches a noise efficiency factor of 1.44. The EOG mode achieves a 39.5 dB gain and a 22.4 Hz bandwidth while presenting an input-referred noise of 0.829 μV corresponding to a noise efficiency factor of 6.37. For both modes, the supply voltage is 1.2 V and the circuit consumes 1 μA.

The layout design of analog integrated circuits has been defying all automation attempts, and it is still primarily a handcrafting process carried by circuit designers on traditional layout editing frameworks. This paper presents a toolbox based on deep learning techniques and a sturdy graphical user interface to assist designers during that process. The underlying mechanism of this toolbox relies on a simple pairwise device interaction circuit description, i.e., the circuits’ topological constraints, to propose valid floorplan solutions for block-level structures, including topologies and deep nanometer technology nodes not used for its training, at push-button speed. Despite its automatic functionalities, the toolbox is focused on explainable artificial intelligence, involving the designer in the synthesis flow via filtering and editing options over the candidate floorplan solutions. This constant state of human-machine feedback environment turns the designer aware of the impact of each device’s position change and inherent tradeoffs while suggesting subsequent moves, ultimately increasing the designers’ productivity in this time-consuming and iterative task. Finally, the toolbox is shown to instantly generate floorplans with similar or better constraint fulfilment than human designed solutions for state-of-the-art analog circuit blocks.

This paper presents the behavioral modeling of three circuit architectures, which are suitable for heartbeat detection in wireless healthcare applications. The developed front-end models implement an analog system that detects the heartbeats for lower power consumption and higher detection accuracy without digital signal processing. Therefore, the circuit blocks and their critical specifications specifically regarding the noise and bandwidth are evaluated. The architectures are implemented in Verilog-A and their behavior simulations use real electrocardiogram (ECG) signals with different characteristics and conditions. All architectures have amplification, band-pass and notch response blocks as their first three stages. Then, the first circuit architecture detects the heartbeat using an adaptive threshold based on a pulse width approach. The second heartbeat detection scheme finds the maximum and minimum values of each beat using a sample-and-hold-based peak detector. The third model uses a similar peak detection scheme, but delays the analog signal for better precision. The simulation results show that all models can detect heartbeats when the input noise is less than 20 μ V , the third having the highest noise tolerance of around 50 μ V . For the ECG signal to maintain its characteristics with respect to its positive and negative peak, the bandpass response should present a low cutoff frequency below 10 Hz.

This research describes the design of a fully CMOS-integrated boost DC-DC converter to be supplied by an ultra-low power solar cell for energy harvesting applications. The monolithic system is based on the inductive boost converter, with both the energy storage spiral inductor and the output filter capacitor integrated together with an LC oscillator at 2.65 GHz, to drive both MOSFET switches, in a 110 nm CMOS process. The system delivers 1.2 V for a 10 kΩ load, with an output power of the order of 144 μW. Experimental results also show that the proposed inductor-based fully CMOS DC-DC boost converter has a record low silicon footprint (0.13 mm²) and highest power density (1.1 mW/mm²) when compared with other counterparts resorting to the same boost topology. The fully integrated solution can be used in the power management units of standalone or remote integrated systems, for several applications such as biomedical or IoT, usually characterised for ultra-low voltage photovoltaic applications.