This article presents a 7-bit 900-MS/s multi-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with background offset calibration. Unlike prior works that adopt either four capacitive DACs (CDACs) or interpolated resistive DAC to enable 3-bit/cycle operation, the proposed technique uses only two CDACs to realize the same functionality. The number of CDACs is reduced by embedding gain inside the two-path comparators, resulting in reduced power, area, and input loading. In addition, the built-in redundancy relaxes the accuracy requirements for DAC settling and comparators. On-chip background offset calibration with narrow pulse charge sharing is used to further improve the ADC linearity. The prototype fabricated in 40-nm LP CMOS achieves an SNDR of 39.7 dB at Nyquist input and consumes 2.6 mW including on-chip calibration, leading to a Walden FoM of 36.6 fJ/conversion-step.

This brief presents a high-speed successive approximation register analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can be tolerated and settling time can thus be reduced. In addition, split capacitor technology has also been adopted to further boost the conversion speed. With split switching method, no common mode voltage is needed in DAC reset phase and dynamic offset can be removed as well. Full adder-based encoder is employed to convert the raw 11-bit to 10-bit binary codes, showing less power penalty. The prototype ADC fabricated in 65-nm CMOS achieves 51.1 dB SNDR and 62.3 dB SFDR at 150-MS/s sampling rate. It consumes 1.4 mW, resulting in a Walden figure of merit of 31.8 fJ/conversion step.

This work presents an ultralow-power 10-bit 200-kS/s single-ended successive approximation register (SAR) analog-to-digital converter (ADC) for implantable biosensor applications. A high energy- and area-efficient switching scheme is proposed, which realizes 95.4% energy saving in a digital-to-analog converter (DAC) switching and two times DAC area reduction compared to the conventional single-ended SAR ADC. The common-mode variation in the proposed scheme is input-independent, resulting in a reduced dynamic offset and harmonic distortion. Besides, a low offset and low kickback noise dynamic comparator with P-type input pair is realized. The prototype is fabricated in 65-nm CMOS technology, consuming 94 nW at 0.6-V supply and occupying a 0.02-mm ² active area. With the Nyquist input frequency, it achieves the signal to noise and distortion ratio (SNDR) of 56.42 dB, leading to a Walden figure of merit (FoM) of 0.87 fJ/conv.-step.

This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive derivative-based correction, employing low filter taps and resulting in hardware reduction. Two reference voltage generators are implemented on-chip to provide a stable reference voltage for the sub-ADCs, enhancing the reliability and robustness of the circuits. The TI-ADC prototype is fabricated in 65 nm CMOS process and occupies an area of 0.69 mm2. The measurement results show that at a sampling rate of 600 MS/s the ADC achieves a 49 dB SNDR after calibration while dissipating 34 mW from a 1.2/2.5 V supply.

This article presents a 12-bit 1.5-GS/s single-channel pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The ADC leverages a pipelined residue amplification (RA) stage scheme, early quantization technique, and fast differential ring amplifier (ringamp) to achieve high speed and high power efficiency simultaneously. The pipelined RA stage scheme allows the RA and SAR conversion to run in parallel for a fast pipelining operation and a relaxed residue amplifier’s bandwidth requirement, thus alleviating the speed bottleneck of the pipelined SAR ADCs. The early quantization technique reduces the timing budget of the SAR conversion phase, thereby further improving the ADC speed. The differential ringamp with a short settling time and low common-mode gain guarantees the high accuracy and high speed of the critical RA. Furthermore, a flexible digital-to-analog-converter (DAC) topology combining the scaling capacitor and bridge capacitor is employed to align the quantization range avoiding large overheads. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 21.3 mW at 1.5 GS/s. The signal-to-noise-and-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) are 58.5 and 74.5 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 20.7 fJ/conversion step and a Schreier FoM of 164 dB.