This paper presents the fabrication, experimental analysis and electrical characterization of the first functional SiC superjunction (SJ) device. A trench-etching-and-sidewall-implant method has been developed to implement the SJ principle on a SiC Schottky diode. Several key process steps, including deep trench etching, ion implantation, and high-temperature annealing, are found to have noticeable influences on the device performances. The corresponding influences are studied by both simulation-aided theoretical analysis and experimental measurements. The highest measured cell blocking voltage was 1350 V, which achieves 95% of the simulated blocking voltage for the perfectly charge-balanced SJ structure. The measured device specific on-resistance was 0.92 mΩ · cm ² . The SJ drift region specific on-resistance as low as 0.32 mΩ · cm ² was obtained after subtracting the substrate resistance. This result successfully breaks the SiC 1-D unipolar limit.

This article presents the design and fabrication results of the silicon carbide (SiC) super-junction Schottky barrier diode (SBD). The impact of two key device structure parameters, i.e., mesa width (MW) and trench width (TW), on the device forward and reverse performance is studied by numeric simulations and measurements. Furthermore, a simple and efficient termination structure, i.e., wide-trench termination, is proposed to protect the device edge. With this termination, the simulated device breakdown voltage is significantly increased from 1423 to 2600 V with a wide-trench termination width (WTW) larger than $20~\mu \text{m}$ . The outermost MW (OMW) of the transition region is also investigated. It is found that the narrower OMW can mitigate the electric field crowding at the top of the outermost mesa and reduce the electrical stress of the dielectric. Devices with different structural parameters are fabricated and measured. The device with WTW $= 50\,\,\mu \text{m}$ and the optimum OMW demonstrates the highest breakdown voltage of 1920 V. The specific ON-resistance ( ${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$ ) of this device is 1.6 $\text{m}\Omega \cdot $ cm ² . Subtracting the substrate resistance, the ${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$ is only 1.2 $\text{m}\Omega \cdot $ cm ² . Such device performance successfully breaks the theoretical 1-D limit of the SiC unipolar device. Furthermore, the leakage current path of the fabricated device is investigated by thermal emission microscope (EMMI). Future improvements to reduce the leakage current are also provided.

Termination design for 4H-SiC super-junction devices based on “trench-etching and implantation” technology, has been discussed through 3D numeric simulations and experiments. It is found that the existing design concept of super-junction termination extension (SJTE) structure is no longer capable of blocking high voltage due to the hole accumulation on the trench sidewall. In order to provide sufficient protection for the device edge, a novel device structure, i.e., hybrid termination of wide trench and SJTE (WT-SJTE), is proposed. With such WT-SJTE structure, the simulated device breakdown voltage can be improved from 700V to 800V. Furthermore, through the narrow termination mesa design, as predicted by numeric simulations, a noticeable improvement were measured, and a breakdown voltage of 960V was experimentally demonstrated. These results show the effectiveness of the WT-SJTE with such narrow termination mesa design.

Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of $1.8 \mu \text{m}$ and active area of 0.104 mm ² achieves a breakdown voltage of 1086 V and a specific ON-resistance of 0.98 $\text{m}\Omega \,\cdot $ cm ² . The first-quadrant output and transfer characteristics are presented, from which the ON-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the ${x}$ -direction and trapezoidal mesas in the ${y}$ -direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop ( $\vert {V}_{\text{on}}\vert $ ) and the maximum current before gate junction turn-on ( ${J}_{\text{umax}}$ ). The third-quadrant performance can be improved by using forward-on gate voltage, a $\vert {V}_{\text{on}}\vert $ lower than 0.2 V (at 100 A/cm ² ) and a ${J}_{\text{umax}}$ larger than 500 A/cm ² are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications.

This paper investigates and compares the static performance and short-circuit (SC) robustness of 1200 V SiC MOSFETs with varying JFET widths (W_JFET = 2.0–5.0 μm). Short-circuit measurements as well as electrical-thermal simulations are used to identify thermal distribution and maximum electrical field, providing valuable insights into the design limits. The devices under test (DUTs) with narrow and wide W_JFET exhibit different failure mechanisms under SC stress. After the short-circuit failure, interlayer dielectric (ILD) cracks are observed in DUTs with narrow JFET width (W_JFET < 3 μm). In contrast, it is discovered that the burn mark is located in the channel region of the device with a wide JFET width. Moreover, the short-circuit withstand time (SCWT) of DUTs with narrow and wide W_JFET exhibits varying trends under high temperature conditions (100 °C). These results can help verify the different failure mechanisms and determine an optimal JFET design to improve the trade-off between the static performance and SC ruggedness of the SiC MOSFETs.