Silicon carbide (SiC) devices enable more compact and efficient design of applications such as traction inverters and rectifiers. With miniaturization of power electronics, volume and weight of heatsink or cold plate occupies a significant portion. So, thermal design, especially power loss evaluation, is crucial to the whole system. Analytical switching model based on datasheet parameters is usually adopted to evaluate devices' switching loss due to its convenience. However, when applied on SiC metal-oxide-semiconductor field-effect-transistors (MOSFETs), turn-on waveforms of conventional analytical switching model show obvious discrepancy from experiments at both current rising and voltage falling stages. The transfer and capacitance characteristics from datasheet are responsible for that. Due to short channel effect and drain-induced barrier lowering, transfer characteristic during turn on period varies with different drain-to-source voltage vds. Cgd during actual turn on period is also different from that on the datasheet. So, considering the actual turn on process, dynamic transfer characteristic and Qgd are proposed and measured in this paper. After these modifications, switching-on waveforms of the analytical switching loss model match the experiments very well, and error of the estimated loss is less than 5%.

In this work, third-quadrant I-V characterization and surge current tests are carried out on SiC asymmetric trench MOSFET (DUT A) and SiC double-trench MOSFET (DUT B) under various gate-source biases (VGS). The surge capability is found to be uninfluenced by VGS for DUT A. However, it has a 71.4% increase when VGS changes from 0V to -5V for DUT B. The I-V characteristics in third quadrant are measured under various VGS. It is found that the channel is open when the source-drain voltage is >2.5V for DUT A and >1.5V for DUT B at VGS=0V. High temperature measurements are also conducted from 298K to 448K. When VGS=0V, the channel current takes up to 50% at 10A source-to-drain current for DUT B, whereas only 10% for DUT A. This could lead to high current/heat density in the channel of DUT B. The transient resistance is also extracted from the surge I-V trajectories and it is higher for DUT B tested under VGS=0V, which will increase the dissipated surge energy. Finally, failure mechanism is analyzed. For DUT A, aluminum melting contributes to the failure at VGS=-5V and VGS=0V. For DUT B tested at VGS=0V, earlier breakdown happens due to gate oxide failure.

In this work, the surge reliability of 1200 V SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) from various manufactures has been investigated in the reverse conduction mode. The surge current tests have been carried out in the channel conduction and non-conduction modes. The experimental results show that the maximum surge currents that the devices can withstand are similar for both cases. It is found that short circuits occurred between the gate and the source in the failed devices. The characteristics of the body diode have also changed after the tests. By measuring the device characteristics after each surge current is applied, it can be concluded that the damages to the gate oxide layer and the body diode occurred only when the maximum surge current is applied. By decapping the failed devices and observing the cross section of the damaged cell, it is found that high temperature caused by excessive current flow through the devices during the surge tests is the main reason for the device failure. Finally, the TCAD simulation of the devices has been carried out to bring insight into the operation of the devices during the surge events.

In this article, the influence of the JFET width and JFET doping concentration on the 1.2-kV planar-gate silicon carbide (SiC) MOSFETs’ static characteristics, C – V characteristics, and short-circuit (SC) reliability is discussed. With the increase of the JFET width, the specific ON-resistance decreases first and then increases (but the quasi-saturated current continues to increase), the blocking voltage decreases, and the reverse capacitance increases. The SC tests under 400-V dc bus voltage are carried out to compare the SC capability of the devices. With the increase of the JFET width, the SC peak current first increases and then decreases, and the SC withstanding time keeps decreasing. The increase of peak current is due to the weaker electric field shielding effect by the P-well. With the further increase of the JFET width, the peak current decreases because the depletion layer appears in the middle position of the JFET region below the gate oxide and the channel density decreases with the wider JFET width. Compared with the winner of the traditional design, the winner with enhanced JFET doping is preferred because it achieves an increased Baliga’s figure of merit (BFOM) by 15.9% and 1/high-frequency figure of merit (HF-FOM) by 84.2% without sacrificing too much SC reliability, which is more competitive.

In this work, the influences of P-well design and turn-off gate-to-source bias on the surge robustness of SiC MOSFET’s body diode are studied. Devices with high and low P-well doping concentration designs are stressed with surge current pulses when the gate-to-source is biased with 0 or −5 V. The gate-to-source bias is found to have effects on the surge capability of the low P-well doping-designed device. In the case of 0-V bias, the channel is prone to turning on and acquires a higher surge capability than the devices under the −5 V. On the other hand, the surge capability of high P-well doping-designed device is found less influenced by the gate-to-source bias. Furthermore, threshold voltage instability after repetitive surge pulses is also investigated. The device with low P-well doping shows better threshold stability due to its lower interface trap density. Based on the results above, a design methodology is proposed from the view of device mechanism and operation condition. Relatively low P-well doping design and negative gate bias are recommended for SiC MOSFET, as they can improve the single-pulse surge robustness of body diode and minimize the threshold voltage instability in repetitive surge pulse events.

In this article, a structure design concept plasma spreading layer (PSL) has been introduced into planar silicon carbide (SiC) MOSFETs. Devices’ static characteristics, gate–drain capacitance ( $\textit{C}_{\text{gd}}\text{)}$ , and short-circuit (SC) robustness are studied with experiments. The PSL structure can increase the breakdown voltage (BV) and reduce $\textit{C}_{\text{gd}}$ of the devices. The MOSFETs with the PSL exhibit an 11.6% higher Baliga’s figure of merit (BFOM) and a 75% higher 1/high-frequency figures-of-merit (HF-FOM). Moreover, they have better SC robustness by 60%, 67%, and 33% under 400-, 600-, and 800-V dc bus voltage than that of the traditional one. Combined with the experimental data and the 3-D simulation results, the MOSFETs with the PSL have enhanced JFET effects, which reduces the electric potential, SC current density, and electric field in the JFET region during the SC process, so as to enhance the SC robustness. The SC failure mechanisms are studied with emission microscope (EMMI) analysis, focused ion beam (FIB) observation, and simulations.