As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore’s era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.

Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot be stored when SRAM is powered off, RRAM technology was introduced into SRAM to realize an SRAM with nonvolatile function. The differential mode was adopted to improve the data restoration speed. Meanwhile, a pre-decoding technology was proposed to realize fast address decoding, and a voltage-mode sensitive amplifier was used to achieve fast amplification of two bit lines, so as to improve the reading speed of the memory. An 8kb nvSRAM was implemented with a CMOS 28 nm 1P9M process. The simulation results show that when the power supply voltage was 0.9 V, the static/read/write noise margin was 0.35 V, 0.16 V and 0.41 V, respectively. The data storage time was 0.21 ns, and restoration time was 0.18 ns. The time for the whole system to read 1 bit of data was 5.2 ns.

As the semiconductor industry enters the post-Moore era, the carbon nanotube field-effect transistor (CNTFET) has become a powerful substitute for silicon-based transistors beyond 5 nm process nodes due to its high mobility, low power consumption, and ultra-thin-body electrical advantages. Carbon-based transistor technology has made significant progress in device manufacture and preparation, but carbon-based process design kits (PDKs) that meet the standards of commercial design tools are still an important bottleneck hindering the development of carbon-based integrated circuits. For the first time, a complete full-custom 90 nm CNTFET PDK is proposed in this paper, which includes Pcells for transistors, resistors, and capacitors; a compact model; DRC/LVS/PEX rules; and a standard cell and timing library. It can support the entire design flow of analog, digital, and mixed-signal carbon-based integrated circuits. To achieve an accurate compact model, the back-gate effect of CNTFETs and the influence of gate/drain voltage on transport probability are analyzed. Then the theoretical formulas for mobility and channel current are established. The comparison of the simulation and test results of CNTFET characteristics proves the accuracy of the compact model. Using this PDK, combined with standard IC design tools and design flow, the circuit and layout of an operational amplifier, SRAM, and 8-bit counter are completed. The simulation results verify the correctness and effectiveness of the PDK, laying a solid foundation for the large-scale industrialization of carbon-based integrated circuits.

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (V_bg) and threshold voltage (V_th) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model.

Recently infrared photodetectors based on low-dimensional semiconductors have developed rapidly. However, due to its poor light absorption and incompatibility with traditional silicon-based readout circuit processes, the sensitivity and integration of such photodetectors are limited. In this work, we proposes a 64 × 64 quantum dot short-wavelength infrared (SWIR) photodetector composed of carbon nanotube thin film transistor (CNT TFT) and silicon-based ROIC. CNT TFT's gate is constructed by PbS colloidal quantum dots (PbS CQDs) which improve the absorption rate of infrared light. The generated photovoltage is amplified and converted in situ by CNT TFT. Notably, under infrared radiation of 1300 nm, the noise equivalent current reach up to 1.25*10⁻¹³A/Hz^1/2. At a drain-source bias (Vds)= -0.1 V. The device exhibits detectivity of 5.6*10¹³ Jones and a fast response of 0.57 ms. The silicon-based ROIC is implemented by CMOS 0.18um process, with a power supply voltage of 1.8 V. It mainly includes a programmable integrator, a sampling and holding circuit, and a 10bit/2.5 MHz successive approximation analog-to-digital converter (SAR ADC). The programmable integrator has four levels of integral gain to meet the application requirements of different infrared light intensities. The experiment results show that the imaging function of the overall photodetector is correct, laying the foundation for the development of carbon-silicon based heterojunction integrated photodetector in the future.

The creation of carbon nanotubes has sparked a paradigm shift in the post-silicon era because of their decent electronic and optical properties. However, interface traps pose an obstacle in the realization of high-performance carbon nanotube field-effect transistors (CNTFETs). Herein, we systematically investigate the C−V characteristics of CNTFETs and propose a small-signal equivalent model to decouple the effects arising from interface traps. Moreover, intrinsic parameters associated with interface traps can be feasibly extracted using this approach. An analytical capacitance model is further developed to be incorporated into the well-established CNTFET virtual source model, and excellent agreement has been achieved between our simulation and the measured results of the as-fabricated MOSCAP. The models developed here help to gain insight into the physical properties of high-κ dielectric interface traps subjected to different processes and inform strategies to achieve high-performance CNTFETs.