In this article, we present for the first time to our knowledge, a DWDM 16×16 silicon photonic cyclic-frequency AWGR device. The AWGR features a channel spacing of 1.06 nm (189 GHz), a free spectral range of 17.80 nm (3.16 THz) and a 3-dB channel bandwidth of 0.65 nm (116 GHz). Its proper cyclic-frequency operation was experimentally verified for all 16×16 channels with channel peak insertion loss values in the range of 3.90 dB to 8.37 dB, yielding a channel loss non-uniformity of 4.47 dB. Its compact footprint of 0.27 mm × 0.71 mm and its low crosstalk value of 21.65 dB highlight its potential for employment in future AWGR-based interconnect schemes in O-band.

A silicon photonic circuit comprising all the building blocks necessary to demonstrate optical communication between two sockets interconnected through an Arrayed Waveguide Grating Router is reported. The paper focuses on the robustness of the interconnection scheme to the unavoidable wavelength and thermal fluctuations observed in real datacenter environments. To improve the reliability of the system, a feedback control mechanism, based on ContactLess Integrated Photonic Probes and heater actuators, is added to the interconnection to monitor in parallel the working point of each sensitive device and keep it locked in real-time. Experimental results demonstrate successful operations in a 30 Gbit/s data routing scenario at 510-11 bit error rate, irrespective of sudden wavelength shifts of up to 200 pm or of iterated thermal variations in a 10 C temperature range, with a recovery time of around 30 ms. These results prove that AWGR-based interconnections equipped with real-time drift compensation systems can be a viable option in multi-socket layouts even in highly demanding environments.

The increasing need for more efficient communication networks has been the main driving force for the development of complex photonic integration circuits combining active and passive building blocks towards advanced functionality. However, this perpetual effort comes with the cost of additive power losses and the research community has resorted to the investigation of different materials to establish efficient on-chip amplification. Among the different proposals, erbium-doped waveguide amplifiers appear to be a promising solution for high performance transmission in the C-band band with low fabrication cost, due to their CMOS compatibility and integration potential with the silicon\silicon nitride photonic platforms. In this paper we provide a holistic study for high-speed WDM transmission capabilities of a monolithically integrated Al₂O₃:Er³⁺ spiral waveguide amplifier co-integrated with Si₃N₄ components, providing a static characterization and a dynamic evaluation for (a) 4 × 40 Gbps, (b) 8 × 40 Gbps and (c) 8×60 Gbps WDM transmissions achieving clearly open eye diagram in all cases. The active region of the erbium doped waveguide amplifier consists of a 5.9 cm Al₂O₃:Er³⁺ spiral adiabatically coupled to passive Si₃N₄ waveguides combined with on chip 980 nm/1550 nm WDM Multiplexers/Demultiplexers. Experimental results reveal bit-error rate values below the KR4-FEC limit of 2×10^-5 for all channels, without any DSP applied on the transmitter or receiver side for a 4×40 Gbps and 8×40 Gbps data stream transmission.

Duringthe past years, incorporating Οptical Circuit Switches (OCS) in high-bandwidth optical interconnects has outlined the critical challenges of achieving ultra-low fiber-to-fiber losses (FtF) and constantly decreasing costs for Photonic Integrated Circuits (PICs). This work aims to simultaneously satisfy both the low-loss and low-cost requirements by bringing two of the most successful example-technologies in the history of optics, i.e., EDFAs and ROADMs to a common Si ₃ N ₄ platform. In particular, the proof-of-concept operation of a lossless four-port Silicon Photonic (SiPho) ROADM is experimentally presented for the first time based on two PIC prototypes on a Si ₃ N ₄ platform, including a monolithic-integrated 5.9 cm-long spiral Al ₂ O ₃ :Er ³⁺ Erbium Doped Waveguide Amplifier (EDWA) with 15 dB signal enhancement capabilities and a lattice MZI-interleaver ROAM layout with 100 GHz channel spacing. Considering an ultra-low 2.55 dB FtF loss of the ROADM along with 0.5 dB loss for each of the two coupling-interfaces between the Si ₃ N ₄ and Al ₂ O ₃ :Er ³⁺ waveguide layers, a cumulative loss of 3.55 dB is obtained, which can be compensated by the 3.6 dB net gain provided by the EDWA to four incoming WDM signals of −1.7 dBm/channel. Lossless wavelength-routing operation is validated at up to 240 Gb/s WDM (4λ × 60 Gb/s) data traffic, while the cascadability of the proposed device is benchmarked in a realistic two-stage optical bus topology with 10 km single mode fiber that selectively routes 4λ × 25 Gb/s WDM data channels to any of its eight Drop output ports. This work forms the first demonstration of lossless ROADM operation exclusively on SiPho technology, highlighting a promising roadmap for large scale SiPho switching matrices and more complex PICs co-integrated with EDWAs.

During the past years, optical memories have emerged as the main way to enable fast access times and increased memory bandwidth in synergy with optical interconnections. The migration, however, to fully functional and practical optical RAMs and cache memories will require an additional yet essential step: Optical memories have to get organized into an optical memory subsystem for delivering seamless cooperation between storage and peripheral decoding units, exploiting also the wavelength dimension for efficient RAM architectural layouts. In this paper we demonstrate the first experimentally verified Wavelength Division Multiplexing (WDM) -enabled optical RAM Row subsystem comprising both the peripheral decoding circuitry and a 4-bit optical RAM Row for storing 20Gb/s 4-bit WDM-formatted optical data words. The proposed scheme comprises a single shared multi-λ Semiconductor Optical Amplifier Mach-Zehnder Interferometer (SOA-MZI) Access Gate (AG) for granting access-control to the complete RAM Row, a passive Column Decoder (CD) that directs the incoming WDM-formatted data words to the respective RAM cells that are in turn based on four broadband Indium Phosphide (InP) photonic integrated Flip-Flops (FFs). Our experimental verification firstly investigates the broadband capability of the elementary InP monolithic RAM cell at 5 Gb/s, revealing error-free Write functionality with <4.5 dB power penalty across the whole C-band confirming in this way the potential of efficient scaling to multi-cell WDM-enabled RAMs. Then, experimental validation of the complete 4-bit WDM-enabled optical RAM Row with 20 Gb/s WDM-formatted data words is performed, featuring simultaneous Access gating, decoding and storage operation for all four RAM cells, having a peak power penalty within the range of [4.6-5.6] dB for Write and [2.2-2.9] dB for Read functionalities, respectively, at a Bit Error Rate of 10 ⁻⁹ .