This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field.

Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage, as well as performing defect localization in these circuits, has proven to be a difficult/expensive task, even with sophisticated testing circuitry. The ISO 26262 standard for functional safety (FuSa) includes the stringent requirement that an automotive IC must have a very high defect coverage. This reinforces the need to ensure the functionality of analog and mixed (AMS) circuits, especially in mission critical applications. This paper presents an all-digital op amp defect detection, diagnosis, and localization method that can be used both for production and in-field tests and discusses various implementation of the proposed method. We validated our results using extensive transistor-level simulations of multiple op amp architectures using TSMC 180 nm technology. Across op amp architectures and multiple implementation approaches, we achieved a worst-case and best-case defect coverage of 94.5% and 99%, respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

This article presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least third-order gradient effects. A new analysis leads to mathematical constraints on 1-D layouts that meet the required integer ratio and cancel second-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-D layouts that cancel higher-order gradients. We demonstrate our proposed methodology on current sense transistors interspersed in active power transistors. Legato electrothermal simulation show our proposed approach, respectively, improves worst-case matching accuracy about a factor of 9.9 and 7.15 when compared to a common centroid (CC) and interdigitated (ID) pattern in the presence of gradients effects. Furthermore, we discuss evaluation metrics that can be used to select one of multiple gradient canceling layouts for any fixed rectangular grid and device application.

Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial building blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage as well as performing diagnosis and defect localization in these circuits has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. ISO26262 Standard for functional safety (FuSa) places stringent requirement that an automotive IC must have a very high defect coverage (usually greater than 90%). This reinforce the need to improve the robustness in the design of analog and mixed signal (AMS) circuits to ensure their reliability especially if they are used in mission critical industries. This paper presents a simple defect detection, diagnosis, and localization method for op amps including Widlar current reference and biasing circuitry and can be used both for production and in-field tests for online health monitoring to ensure continued reliability during integrated circuits’ (IC) lifetime. We rigorously validate all our results using extensive transistor-level simulations of two op amps architectures (folded cascode and telescopic) designed in MUSE TSMC 180nm technology. For the folded cascode op amp, the proposed method achieves a worst-case defect coverage of 94.5% and a best-case coverage of 98%. Similarly for the telescopic op amp, the proposed method attains a worst- and best-case defect coverage of 97% and 99% respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DCDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DCDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DCDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DCDC a promising advancement in the field.