This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field.

A modified sliding mode controller with continuous switching is proposed for a class of nonlinear multi-input systems. The control design consists of first choosing a set of suitable sliding sectors, instead of conventional sliding surfaces, then constructing a continuous switching controller. It is shown that the global attractiveness and stability of the sliding sectors are guaranteed with the continuous switching control strategy. While retaining the robustness property of general sliding mode control, the modified sliding mode controller provides much smoother control signals. Trajectory control of a two-link robot and set point control of a nonlinear two-input system are investigated to show the effectiveness of the new method.

This article presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least third-order gradient effects. A new analysis leads to mathematical constraints on 1-D layouts that meet the required integer ratio and cancel second-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-D layouts that cancel higher-order gradients. We demonstrate our proposed methodology on current sense transistors interspersed in active power transistors. Legato electrothermal simulation show our proposed approach, respectively, improves worst-case matching accuracy about a factor of 9.9 and 7.15 when compared to a common centroid (CC) and interdigitated (ID) pattern in the presence of gradients effects. Furthermore, we discuss evaluation metrics that can be used to select one of multiple gradient canceling layouts for any fixed rectangular grid and device application.

Accurate minimum operating voltage (V_min) prediction is a critical element in manufacturing tests. Conventional methods lack coverage guarantees in interval predictions. Conformal Prediction (CP), a distribution-free machine learning approach, excels in providing rigorous coverage guarantees for interval predictions. However, standard CP predictors may fail due to a lack of knowledge of process variations. We address this challenge by providing principled conformalized interval prediction in the presence of process variations with high data efficiency, where the data from a few additional chips is utilized for calibration. We demonstrate the superiority of the proposed method on industrial 16nm chip data.

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DCDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DCDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DCDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DCDC a promising advancement in the field.