This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC-based voltage-controlled oscillator, are proposed to simultaneously reduce the PLL integrated jitter and the jitter variation over supply voltage variation. Fabricated in 40-nm CMOS process with a core active area of 0.24 mm², the LVSSPLL operates at 0.65-V supply and achieves 12-16-GHz tuning range, 56.4-fs integrated jitter at 14 GHz, 7.2-mW power consumption, and -256.4-dB figure-of-merit (FoM). The measured integrated jitter variation is less than 14.5 fs within the supply voltage range from 0.62 to 0.7 V, which shows robustness over supply voltage variation.

This article presents a 50-Gb/s optical transmitter (TX), consisting of a 40-nm distributed CMOS driver and a 180-nm silicon-photonic modulator. A lumped-segment Mach–Zehnder modulator (LS-MZM) is developed for high bandwidth (BW) four-level pulse amplitude (PAM-4) modulation. A multi-segment driver with limiting outputs is co-designed, which is distributed into each LS-MZM segment. By grouping these LS-MSM segments in a thermometer code, high-linearity modulation is realized without the need of power-hungry high-swing linear drivers. To improve the optical PAM-4 signal integrity, in-segment multiplexing along with clock phase interpolation is adopted to synchronize the electrical and optical signals across all segments. The hybrid coupling between the driver and modulator is devised to boost the BW of the high-speed data path, while a half-rate clock and data recovery (CDR) circuit is integrated to remove the accumulated jitter. Measurements show that the TX exhibits an extinction ratio (ER) of up to 9.8 dB and a 0.99 ratio of the level mismatch. A figure-of-merit (FoM) of 1.39 pJ/bit/dB corresponds to a 682-mW power, which can be further reduced by 40%, at the cost of a degraded ER of 4 dB. The PAM-4 CDR helps to achieve $< 10^{-12}$ BER and >0.1- $\text{U}I_{\mathrm {pp}}$ jitter tolerance (JTOL) from 10 to 100 MHz.

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of <; 10 ^-12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs.

This paper proposes a low-voltage low-power hybrid digital phase-locked loop (LVHDPLL). It adopts a loop bandwidth-tracking technique to keep the loop bandwidth almost constant in order to make the LVHDPLL operate robustly over process, voltage, and temperature variation. We also propose the technique of dynamical control of clock frequency for digital loop filter, and the gated source-switched charge pump to save the power consumption. The LVHDPLL is implemented in a 65-nm CMOS process. It can generate frequency from 0.9 to 2.25 GHz (1.35 GHz) at 0.75-V (0.6 V) supply voltage. The maximum power consumption is 0.43mW at 0.75 V and 0.21 mW at 0.6 V. The power efficiency is 0.191 and 0.156 mW/GHz at 0.75- and 0.6-V supply, respectively. The figure of merit is -228 and -227.4 dB at 0.75and 0.6-V supply, respectively. The loop bandwidth variation over all covered frequency range is ±7.5%. From 0 °C to 70 °C, the loop bandwidth variation and rms jitter variation are less than 6.1% and 8.8%, respectively. The loop bandwidth variation and rms jitter variation over supply variation (-0.03 to 0.05 V) is less than 7.1% and 9.5%, respectively. This LVHDPLL shows robustness over temperature and supply voltage variation.

This paper presents a hybrid-integrated optical transceiver front-end for beyond-400G short-reach optical links. A pair of the monolithic 8-channel laser drivers and the trans-impedance amplifier (TIA) is developed in 180nm SiGe BiCMOS, incorporating arrayed Vertical-Cavity-Surface- Emitting Lasers and photo-detectors. The driver uses a $2^{\mathrm {nd}}$ -order continuous-time linear equalizer (CTLE) to compensate for the channel loss with a nonlinear frequency response. Both the inductive peaking and RC-degeneration are embedded at the output stage to extend the optical modulation bandwidth (BW). The series-peaking and multi-stage distributed CTLE are combined in a resistive feedback TIA topology for improved BW and linearity. Measurement results show up to 100-Gb/s PAM-4 electrical eyes of the driver and TIA. The optical transmitter front-end operates 56 Gb/s, 4.1-dB extinction ratio, and 6.6-pJ/bit power efficiency, while the optical receiver front-end achieves 56-Gb/s, $10^{-6}$ bit error rate, and 5.9-pJ/bit power efficiency.

This article presents a reconfigurable silicon- photonics transmitter (TX) for short-reach optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver with a 180-nm SOI-CMOS silicon-photonic Mach-Zehnder Modulator (MZM). The driver integrated with in- segment fractional-UI spaced feed-forward equalizer (FFE) is proposed to support the non-return-zero (NRZ) signaling, electrical- and optical-domain 4-level pulse-amplitude modulation (PAM-4) signaling. The driver employs a reconfigurable distributed topology to achieve high swing, wide bandwidth and flexible operation. The MZM is driven differentially in a push-pull configuration for high modulation efficiency. Measurement results show that the proposed TX operates up to 50-Gb/s NRZ data rate with 4-Vppd swing and 1.92-ps RMS jitter. In the optical PAM-4 mode, it reaches 56-Gb/s data rate and achieves >5-dB extinction ratio (ER) at the cost of 10.9-pJ/bit power efficiency.