A fully integrated 76-81-GHz frequency-modulated, continuous-wave (FMCW) radar transceiver (TRX) in a 65-nm CMOS is presented. Two transmitters (TXs) and three receivers (RXs) are integrated for multiple-input multiple-output (MIMO) processing. A 38.5-GHz mixed-mode phase-locked loop (PLL) with reconfigurable loop bandwidth and a frequency doubling scheme are employed to generate the reconfigurable FMCW chirp waveforms. The coarse-to-fine-segmented current DAC is utilized to support sawtooth FMCW chirps with fast frequency ramping-down capability, and the delay lock loop (DLL)-based delay time calibration is used to improve the linearity of the embedded 2-D Vernier time-to-digital converter (TDC). Passive voltage-mode down-conversion is utilized to improve the RX linearity against TX leakage and short-range interference. A bottom-switching Gilbert-type modulator in the TX is proposed to realize the bi-phase modulation, and the magnetically coupled resonator technique is used to effectively expand the link bandwidth. The measurement results show that the FMCW TRX could generate reconfigurable chirps with the bandwidth from 250 MHz to 4 GHz and the period from 30 μs to 10 ms. The root-mean-square (rms) frequency error is 110 kHz for a sawtooth chirp with 4-GHz bandwidth and 300-μs period. The TX maximum output power is 13.4 dBm and is adjustable within 3 dB by reconfiguring its low dropout regulator (LDO) voltage. The RX achieves a 15.3-dB noise figure at 600-kHz IF and a -8.5-dBm RF input-referred P1dB. The overall power consumption is 921 mW, with two TXs and three RXs powered ON. Based on the proposed TRX chip, prototype hardware and a data process algorithm are developed. Real-time experimental results show that the distance and the angular resolution of the MIMO radar achieved are 5 cm and 9$°, respectively.

This article presents a 50-Gb/s optical transmitter (TX), consisting of a 40-nm distributed CMOS driver and a 180-nm silicon-photonic modulator. A lumped-segment Mach–Zehnder modulator (LS-MZM) is developed for high bandwidth (BW) four-level pulse amplitude (PAM-4) modulation. A multi-segment driver with limiting outputs is co-designed, which is distributed into each LS-MZM segment. By grouping these LS-MSM segments in a thermometer code, high-linearity modulation is realized without the need of power-hungry high-swing linear drivers. To improve the optical PAM-4 signal integrity, in-segment multiplexing along with clock phase interpolation is adopted to synchronize the electrical and optical signals across all segments. The hybrid coupling between the driver and modulator is devised to boost the BW of the high-speed data path, while a half-rate clock and data recovery (CDR) circuit is integrated to remove the accumulated jitter. Measurements show that the TX exhibits an extinction ratio (ER) of up to 9.8 dB and a 0.99 ratio of the level mismatch. A figure-of-merit (FoM) of 1.39 pJ/bit/dB corresponds to a 682-mW power, which can be further reduced by 40%, at the cost of a degraded ER of 4 dB. The PAM-4 CDR helps to achieve $< 10^{-12}$ BER and >0.1- $\text{U}I_{\mathrm {pp}}$ jitter tolerance (JTOL) from 10 to 100 MHz.

A 77-GHz frequency-modulated continuous-wave (FMCW) generator is presented for millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a mixed-mode phase-locked loop (PLL). A dual rising-edge fractional-phase detector based on time-to-digital converter (TDC) is proposed to overcome the problem caused by the rising and falling time mismatch. A 2.3 ns detection range, 10 ps resolution Vernier TDC is employed in the detector to cover the two consecutive rising edges with less power consumption. A self-calibrated delay chain is employed in the Vernier TDC to overcome process, voltage and temperature (PVT) variations. Furthermore, sampling-edge selection technique is utilized to avoid the glitch during phase detection. A divider-less frequency error estimator is presented to save area and power. By employing a coarse-fine segmented digital-to-analog converter (DAC), the generator supports triangular and sawtooth-like FMCW chirp with reconfigurable period and bandwidth. An LC voltage- controlled oscillator (VCO) with split varactor is proposed to improve the linear tuning range. Implemented in 65 nm CMOS, the FMCW generator consumes 99 mW power and 0.7 mm x 0.8 mm chip area. The measurement results show that the phase noise from 78.7 GHz carrier is -87.4-dBc/Hz at 1 MHz offset. The measured root-mean-square (RMS) frequency error of a sawtooth-like FMCW chirp with 4 GHz bandwidth and 0.1 ms period is 205 kHz.

This paper presents a hybrid-integrated optical transceiver front-end for beyond-400G short-reach optical links. A pair of the monolithic 8-channel laser drivers and the trans-impedance amplifier (TIA) is developed in 180nm SiGe BiCMOS, incorporating arrayed Vertical-Cavity-Surface- Emitting Lasers and photo-detectors. The driver uses a $2^{\mathrm {nd}}$ -order continuous-time linear equalizer (CTLE) to compensate for the channel loss with a nonlinear frequency response. Both the inductive peaking and RC-degeneration are embedded at the output stage to extend the optical modulation bandwidth (BW). The series-peaking and multi-stage distributed CTLE are combined in a resistive feedback TIA topology for improved BW and linearity. Measurement results show up to 100-Gb/s PAM-4 electrical eyes of the driver and TIA. The optical transmitter front-end operates 56 Gb/s, 4.1-dB extinction ratio, and 6.6-pJ/bit power efficiency, while the optical receiver front-end achieves 56-Gb/s, $10^{-6}$ bit error rate, and 5.9-pJ/bit power efficiency.

This article presents a reconfigurable silicon- photonics transmitter (TX) for short-reach optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver with a 180-nm SOI-CMOS silicon-photonic Mach-Zehnder Modulator (MZM). The driver integrated with in- segment fractional-UI spaced feed-forward equalizer (FFE) is proposed to support the non-return-zero (NRZ) signaling, electrical- and optical-domain 4-level pulse-amplitude modulation (PAM-4) signaling. The driver employs a reconfigurable distributed topology to achieve high swing, wide bandwidth and flexible operation. The MZM is driven differentially in a push-pull configuration for high modulation efficiency. Measurement results show that the proposed TX operates up to 50-Gb/s NRZ data rate with 4-Vppd swing and 1.92-ps RMS jitter. In the optical PAM-4 mode, it reaches 56-Gb/s data rate and achieves >5-dB extinction ratio (ER) at the cost of 10.9-pJ/bit power efficiency.

A 4 $\times$ 112 Gb/s hybrid-integrated silicon photonic (SiPh) transmitter and receiver chipsets are presented for the linear-drive co-packaged optics (CPO). A quad-channel open-collector (OC) driver is co-designed with the arrayed traveling-wave (TW) Mach–Zehnder modulator (MZM) for high bandwidth (BW) and high efficiency. A second-order hybrid passive–active continuous-time linear equalizer (CTLE) is proposed to compensate for the nonlinear channel loss up to 12 dB. A linear trans-impedance amplifier (TIA) is proposed with a T- $\pi$ input network and cascaded embedded CTLE, which boosts the BW while maintaining a flat in-band frequency response. Implemented in 180-nm SiGe BiCMOS, the driver and TIA are measured with over 35-GHz BW. The complete SiPh TRX is built by co-packaging both the driver with MZM and TIA with photodetector (PD). Experimental results show 112-Gb/s PAM-4 eyes of both the E-to-O modulation and O-to-E reception. The OTX achieves a 5-dB optical extinction ratio (ER) and 4.8-pJ/bit power efficiency, while the ORX achieves 67-dB $\Omega$ trans-impedance and 2.95-pJ/bit power efficiency. To emulate CPO application, a compact-size evaluation board (EVB) is made, and four-channel tests are completed.