The growing interest in integrating distributed generation (DG) into the existing power distribution grid, the increase in the penetration levels of renewables, as well as the need to achieve a more efficient, reliable and sustainable grid, are leading to the development of new grid-interfaced power converters such as the solid-state transformer (SST). As current and voltage ratings of commercially available power semiconductor devices are normally below power ratings required in distribution systems (e.g., 13.8 kVrms), multiple modules must be connected in cascade configuration at the highvoltage side to reach higher voltage ratings as well as in parallel at the low-voltage side to achieve high current levels. A new SST topology consisting of modular boost-based threelevel ac-dc converters, medium-frequency transformers with two secondary windings, and four-leg ac-dc converters is presented in this paper. When compared to similar approaches, the proposed topology comprises fewer power conversion stages, lower voltage across the semiconductor devices on the high-voltage side, and lower current flowing through each device on the low-voltage side. These characteristics reduce the number of series-connected modules in the high-voltage side and parallel-connected devices in the low-voltage side. The feasibility of the proposed topology is experimentally validated on a 500 W, 120 Vac/ 48 Vdc scaleddown prototype.

Photoconductive semiconductor switching (PCSS) devices have unique characteristics to address the growing need for electrically isolated, optically gated, picosecond-scale jitter devices capable of operating at high voltage, current, and frequency. The state of the art in material selection, doping, triggering, and system integration in PCSSs is presented. The material properties and doping considerations of GaN, GaAs, SiC, diamond, and β-Ga₂O₃ in the fabrication of PCSS devices are discussed. A review of the current understanding of the physics of the high-gain mode known as lock-on is presented.

With evolving landscape of direct current (DC) power transmission and distribution, a reliable and fast protection against faults is critical. High performance DC solid-state circuit breakers (SSCB) can be designed using silicon carbide (SiC) junction field-effect transistors (JFET), which utilize the device's intrinsic normally- ON characteristic and low ON-resistance. However, for SSCB that require high-voltage (HV) blocking capability, a proper number of JFETs need to be connected in series to achieve the desired voltage blocking rating. It has been conventional to add a controlling normally- OFF transistor, such a metal–oxide–semiconductor field-effect transistor (MOSFET), resulting in a circuit with normally- OFF behavior. However, disparities both in the voltage rating and in the ON-resistance between MOSFETs and JFETs tend to complicate the circuit design, and physically, they may lead to serious localized thermal stresses. Another point of failure may be the degradation of the MOSFETs gate oxide. A significant challenge remains with ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage as it is crucial to prevent irreversible or permanent damages from over-voltage stresses. Therefore, this paper presents a new switch topology, in which a cascaded JFET configuration is operated without using a control MOSFET or other added control device. The dynamic voltage balancing network to synchronize both the JFETs' turn ON and OFF intervals is described analytically. Moreover, a novel static voltage balancing network is proposed to establish equal sharing of the total blocking voltage across the series connection of JFETs while maintaining low power loss.

This research introduces a unique bidirectional dc–dc converter specifically developed for energy storage applications. The proposed circuit topology exhibits a high voltage conversion ratio and a reduced current ripple. On the transformer primary side, a quasi-switched-capacitor (QSC) circuit mitigates voltage stress on switching devices and achieves a 3:1 voltage step-down ratio. The proposed transformer-interleaved circuit on the secondary side features the 2:1 voltage conversion ratio and minimizes the battery current ripple without adding extra switching or magnetic components. The 6:1 voltage conversion contributes to a simpler winding structure, smaller transformer size, and lower transformer loss in high voltage gain application. Furthermore, the reduced current ripple leads to lower battery heat generation and smaller filter bank capacitance, making it suitable for high-density design. The implementation of phase shift control, similar to the dual-active-bridge circuit, serves to regulate the circuit's transferred power. A 1-kW, 300-kHz, 380–420-/20–33-V GaN-based circuit prototype is developed and tested. The tested peak efficiency is 98.5% with a power density of 30.42 W/in ³ .

The main objective of this research work is to develop a new low-cost isolated three-level ac-dc power converter topology with a reduced number of switches. Existing three-level converter topologies change ac power to dc power while maintaining requirements set by international standards for power conversion. These types of converters have significant conduction losses due to high currents in the low-voltage side and high costs, mainly when using several active devices in series or in parallel to achieve high-voltage and high-power levels. The proposed topology replaces the conventional three-level converters in the secondary side by only two controlled devices and four diodes while still maintaining the basic functionality of a three-level converter. Furthermore, simulation results for a 25 kW case study and experimental results on a 900 W scale-down prototype demonstrate the feasibility of the proposed ideas.