Two‐dimensional (2D) materials exhibit fascinating and outstanding optoelectronic properties, laying the foundation for the development of novel optoelectronic devices. However, ultra‐weak light absorption of 2D materials limits the performance of the optoelectronic devices. Here, a structure of MoS ₂ /graphene/Au integrated onto the side‐polished fiber (SPF) is proposed to achieve a high‐performance fiber‐integrated multifunction‐in‐one optoelectronic device. It is found that the device can absorb the transverse magnetic (TM) mode guided in the SPF and generate photocurrents as a polarization‐sensitive photodetector, while the transverse electric (TE) mode passes with low loss through the device, making the device simultaneously a polarizer. In the device, the MoS ₂ film and the Au finger electrode can enhance the TM absorption by 1.75 times and 24.8 times, respectively, thus allowing to achieve high performance: a high photoresponsivity of 2.2 × 10 ⁵ A/W at 1550 nm; the external quantum efficiency (EQE) of 1.76 × 10 ⁷ %; a high photocurrent polarization ratio of 0.686 and a polarization efficiency of 3.9 dB/mm at C‐band. The integration of 2D materials on SPF paves the way to enhance the light–2D material interaction and achieve high performance multifunction‐in‐one fiber‐integrated optoelectronic devices.

Near-field mapping along the surface of an integrated circuit (IC) could reveal the radiated emission source inside by collecting the radiated electromagnetic field. In this article, the radiated emission source localization is first illustrated in a microstrip line model by analyzing the relationship between the physical position of the line and the hot spots of the electromagnetic field distribution along the line surface. The hot spot in each magnetic field distribution does not necessarily correspond to the physical position of the emission source due to the ground plane below. Furthermore, by analogy with the microstrip line model, the localization analysis is applied to a large-scale IC [field-programmable gate array (FPGA)] in a ball grid array package. For the demonstration, four operation states of the FPGA are designed with four general-purpose input–output (GPIO) pins outputting waveforms of different frequencies. By activating the sources in different operation states, it is found that the activated GPIO pins (as emission sources) can be located well by comprehensively analyzing the emission patterns of different components. The experimental results would be instructive to improve the understanding of IC near-field electromagnetic patterns and reasonable to localize an emission source.

Graphene has been widely used in photodetectors; however its photoresponsivity is limited due to the intrinsic low absorption of graphene. To enhance the graphene absorption, a waveguide structure with an extended interaction length and plasmonic resonance with light field enhancement are often employed. However, the operation bandwidth is narrowed when this happens. Here, a novel graphene-based all-fiber photodetector (AFPD) was demonstrated with ultrahigh responsivity over a full near-infrared band. The AFPD benefits from the gold-enhanced absorption when an interdigitated Au electrode is fabricated onto a Graphene-PMMA film covered over a side-polished fiber (SFP). Interestingly, the AFPD shows a photoresponsivity of >1 × 10⁴ A/W and an external quantum efficiency of >4.6 × 10⁶% over a broadband region of 980–1620 nm. The proposed device provides a simple, low-cost, efficient, and robust way to detect optical fiber signals with intriguing capabilities in terms of distributed photodetection and on-line power monitoring, which is highly desirable for a fiber-optic communication system.

In this paper, thermoreflectance microscopy was used to measure the high spatial resolution temperature distribution of the p-GaN HEMT under high power density. The maximum temperature along the GaN channel was located at the drain-side gate edge region. It was found that the thermal resistance (R_th) of the p-GaN HEMT device increased with the increase of channel temperature. The R_th dependence on the temperature was well approximated by a function of R_th~T^a (a = 0.2). The three phonon Umklapp scattering, point mass defects and dislocations scattering mechanisms are suggested contributors to the heat transfer process for the p-GaN HEMT. The impact of bias conditions and gate length on the thermal characteristics of the device was investigated. The behaviour of temperature increasing in the time domain with 50 µs pulse width and different drain bias voltage was analysed. Finally, a field plate structure was demonstrated for improving the device thermal performance.

Hybrid drain-embedded gate injection transistors (HD-GITs) are one of the most promising technologies for normally-off operation. However, the relevant reliability research is relatively lacking. In this paper, comprehensive results of degradation performance in 600V HD-GITs are presented. First, the thermomechanical stress is applied to the device under test (DUT) through an accelerated power cycling test (PCT) setup. Then thermal and electrical parameters shift under the power cycling tests are monitored periodically by the PCT setup and the curve tracer. As can be seen from the measurement results, as the PCT progresses, the device not only exhibits package-level degradation, but chip-level degradation also occurs gradually. Notably, leakage current that increases with degradation appears to be a potential choice for lifetime modeling. Finally, state-of-the-art failure analysis (FA) techniques such as emission microscopy (EMMI), scanning electron microscope (SEM), focused ion beam (FIB) cutting, and others are performed. The results of FAs validated the monitoring data, and the root cause of the degradation of the thermal resistance and electrical parameters was eventually confirmed as the solder degradation and the structural damage of the source and gate. Such an investigation can serve as a valuable reference for the reliability of GaN power devices.

This work systematically investigates the electrostatic discharge (ESD) robustness of Schottky-gate p-GaN high electron mobility transistors (HEMTs) under different gate and drain bias conditions. Gate-terminal ESD robustness is severely compromised under high ${V}_{\text {DS}}$ ( $\ge 40$ V), where synergistic high voltage/current induces thermal runaway, causing irreversible damage. At ${V}_{\text {DS}} =5$ –30 V, trap-dominated ${V}_{\text {TH}}$ shifts (up to 0.68 V) correlate with $1200\times {N}_{\text {it0}}$ increases, partially recoverable over time. With the drain in the floating state, the trap-dominated ${V}_{\text {TH}}$ shift (about 0.47 V) correlate with $140\times {N}_{\text {it}}$ increases, nearly fully recoverable over time. Under the drain-terminal ESD events, the device with the gate in floating state exhibits superior ESD robustness, accompanied by only a 0.12-V negative ${V} _{\text {TH}}$ shift and high ${V}_{\text {HBM}}$ of over 8.61 kV. The devices with gate biased at off/semi-on/on states achieve ${V}_{\text {HBM}}$ from 0.27 to 30 kV, with (semi-on) on-state configurations meeting 2-kV industrial standards. This work bridges the gap in understanding multistress ESD interactions, providing critical insights for optimizing p-GaN HEMT reliability.