In a conventional finite control set model predictive control (FCS-MPC) formulation, active and reactive power control loops rely on the predictive controller, whereas the dc-bus voltage is usually governed by a PI-based control loop. This originates from fact that the dynamic equations for describing the predictions of these variables are heavily coupled. In this paper, a cascade-free FCS-MPC for single-phase grid-connected power converters is presented. The proposed control algorithm is formulated in terms of established dynamic references design, which was originally proposed to directly govern active and reactive power, and dc-voltage in three-phase power converters. In this paper, the dynamic reference design concept is extended to control single-phase grid-connected power converters. The proposed control algorithm does not use instantaneous ac-power calculations; instead, it directly formulates the optimal control problem on the grid-current in the original stationary reference frame. The experimental results obtained with a single-phase grid-connected neutral point clamped (NPC) converter confirm a successful design, where system constraints, e.g., maximum power and weighted switching frequency, are easily taken into account.

Digital signal processors (DSPs) and field-programmable gate arrays (FPGAs) are predominant in the implementation of digital controllers and/or modulators for power converter applications. This paper presents a systematic comparison between these two technologies, depicting the main advantages and drawbacks of each one. Key programming and implementation aspects are addressed in order to give an overall idea of their most important features and allow the comparison between DSP and FPGA devices. A classical linear control strategy for a well-known voltage-source-converter (VSC)-based topology used as Static Compensator (STATCOM) is considered as a driving example to evaluate the performance of both approaches. A proof-of-concept laboratory prototype is separately controlled with the TMS320F2812 DSP and the Spartan-3 XCS1000 FPGA to illustrate the characteristics of both technologies. In the case of the DSP, a virtual floating-point library is used to accelerate the control routines compared to double precision arithmetic. On the other hand, two approaches are developed for the FPGA implementation, the first one reduces the hardware utilization and the second one reduces the computation time. Even though both boards can successfully control the STATCOM, results show that the FPGA achieves the best computation time thanks to the high degree of parallelism available on the device.

Cascaded H-bridge multilevel (CHB-ML) inverters are an attractive alternative for supplying power to ac grids as they have high reliability and offer an acceptable quality of voltage at their output terminals. In order to achieve efficient operation in these CHB-ML inverters, they must work at low switching frequencies. The finite-control set model predictive control (FCS-MPC) scheme is a very intuitive strategy for controlling this type of converter, but traditional FCS-MPC algorithms generally have a steady-state error when operating at low sampling frequencies and/or if there are parameters mismatch in the prediction model, regarding those of the real system. In this article, a grid-connected CHB-ML inverter that uses an improved FCS-MPC scheme is proposed. The proposed strategy eliminates the steady-state error in an MPC operating at low sampling frequencies and maintains correct operation when a change in the control reference occurs. Experimental results from a grid-connected CHB-ML inverter with three units (seven levels) demonstrate the feasibility of the proposal.

Modular current source converters (MCSCs) have been proposed as an alternative method for increasing the power range of medium voltage PWM AC drives. MCSCs are built by stacking parallel current source converters. Two advantages that make MCSCs attractive are: (a) extended current/voltage ratings beyond the device ratings and (b) simplicity in balancing the DC link current in each module. This can be accomplished using two optimized modulating patterns that have been proposed for such topologies: (a) multilevel selective harmonic elimination (MSHE) and (b) displaced selective harmonic elimination (DSHE). Both techniques are based on SHE patterns but there are slight differences in their digital implementation due to the way they generate the harmonic cancellation. Furthermore, when these techniques are used in the rectifier stage, it is reported that MSHE and DSHE do not eliminate all the unwanted harmonics due to practical issues such as changes in the modulating indexes to control the DC link currents. This work compares the operation of DSHE and MSHE when used in rectifiers of an MCSC in terms of execution time, robustness to poor sampling frequency, and quality of harmonic profiles on AC input currents under different operating conditions. Experimental results are presented to validate the theoretical considerations.

This paper extends the use of the versatile buck-boost converter to power manage a parallel hybrid system topology as an alternative to the well-known serial hybrid (SH) topology and the most recent series-parallel hybrid (SPH) topology. These systems utilize a proton exchange membrane fuel cell as the primary source in combination with an auxiliary storage device (ASD), and the selected converter is in charge of the power management between the sources (fuel cell or ASD) and the load. Therefore, the converter has a very important role in the system since it is responsible of ensuring a dc-bus voltage regulation with a safe and reliable operation of the entire system while also guarantee a high power conversion efficiency. Hence, this is the third topology, where the coupled-inductor dc-dc buck-boost converter is studied to demonstrate and exploit its advantages such as noninverting voltage step-up and step-down, high efficiency, regulation of input and output currents and low ripple values, and the ability to change from input to output current regulation loop, suddenly and smoothly, and vice versa. In order to determine which topology (SH, PH, or SPH) exhibits the highest power conversion efficiency under a certain load profile, it is important to ensure a fair efficiency comparison that will only reflect the properties of the topology and not its individual components. Therefore, the same design criteria, the same control, and the same components were used for all the studied topologies. Simulation and experimental results have been validated on a 48-V 1200-W dc bus.

A discrete-time linear control strategy for a multilevel three-phase unified power quality conditioner (UPQC) based on single-phase power cells is presented. The multi-variable, nonlinear, and coupled features of these topologies make the control strategy design a difficult task. Controlling this kind of system with single-variable linear controllers-as proposed in this work-presents significant advantages compared with other approaches as simplicity in the design steps due to the large amount of tools developed for this kind of schemes. Particularly, a classic design method based on the root locus approach is used to choose the controllers parameters in order to achieve a given dynamical behavior. Compensation of reactive power and fundamental frequency disturbances is presented in this paper as part of a general control strategy for multilevel active power filters. The proposed control strategy is implemented on the TMS320C6713 DSP-based system for a low-power laboratory prototype, and thus the controllers design is carried out on the discrete-time and -frequency domain. Also, due to the inherent asymmetries among the power cells in a modular topology, a dedicated local control strategy is proposed to ensure a symmetrical distribution of the power among the power cells. This feature allows the semiconductor devices of each module to operate under the same voltage and current ratings. Simulated and experimental results showing stationary and transient conditions demonstrate the feasibility of the control scheme.