Ionic electroactive polymer (IEAP) actuators that are driven by electrical stimuli have been widely investigated for use in practical applications. However, conventional electrodes in IEAP actuators have a serious drawback of poor durability under long-term actuation in open air, mainly because of leakage of the inner electrolyte and hydrated cations through surface cracks on the metallic electrodes. To overcome this problem, a top priority is developing new high-performance ionic polymer actuators with graphene electrodes that have superior mechanical, electrical conductivity, and electromechanical properties. However, the task is made difficultby issues such as the low electrical conductivity of graphene (G). The percolation network of silver nanowires (Ag-NWs) is believed to enhance the conductivity of graphene, while poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS), which exhibits excellent stability under ambient conditions, is expected to improve the actuation performance of IEAP actuators. In this study, we developed a very fast, stable, and durable IEAP actuator by employing electrodes made of a nanocomposite comprising PEDOT:PSS and graphene–Ag-NWs (P/(G–Ag)). The cost-effective P/(G–Ag) electrodes with high electrical conductivity displayed a smooth surface resulting from the PEDOT:PSS coating, which prevented oxidation of the surface upon exposure to air, and showedstrong bonding between the ionic polymer and the electrode surface. More interestingly, the proposed IEAP actuator based on the P/G–Ag electrode can be used in active biomedical devices, biomimetic robots, wearable electronics, and flexible soft electronics.

Despite the advantages of ternary logic, it has suffered from excessive transistor count and limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) based on negative capacitance carbon nanotube field-effect transistors (NC-CNTFETs). By harnessing the negative differential resistance effect in NC-CNTFETs, the proposed design is similar to a conventional volatile binary FF regarding the number of transistors and control signals. During a scheduled power gating or a sudden power outage, the proposed ternary FF benefits from an auto-backup/auto-restore capability without employing any additional transistors, nonvolatile devices, or control signals. This leads to zero device overhead, which is a breakthrough in designing nonvolatile memory circuits. On the other hand, the back-to-back slave latch’s hysteretic behavior provides an extraordinary static noise margin that transcends the noise margin of both conventional ternary and binary latches. The simulation results indicate that eliminating additional backup and restore circuitries provides 43% improvements in transistor count, 59% improvements in power saving and 98% improvements in energy-saving than state-of-the-art binary and ternary FFs. Moreover, the proposed design presents a 1.5 times higher static noise margin than the conventional binary and ternary FFs. Our proposed approach opens new doors in realizing ultra-efficient nonvolatile ternary circuits and systems in neuromorphic applications using ferroelectric-based transistors.

In designing neuromorphic circuits and systems, developing compact and energy-efficient neuron and synapse circuits is essential for high-performance on-chip neural architectures. Toward that end, this work utilizes the advanced low-power and compact 7nm FinFET technology to design leaky integrate-and-fire (LIF) neuron and spike-timing-dependent plasticity (STDP) circuits. In the proposed STDP circuit, only six FinFETs and three small capacitors (two 10fF and 20fF) have been utilized to realize STDP learning. Moreover, 12 transistors and two capacitors (20fF) have been employed for designing the LIF neuron circuit. The evaluation results demonstrate that besides 60% area saving, the proposed STDP circuit achieves 68% improvement in total average power consumption and 43% lower energy dissipation compared to previous works. The proposed LIF neuron circuit demonstrates 34% area saving, 46% power, and 40% energy saving compared to its counterparts. The neuron can also tune the firing frequency within 5MHz-330MHz using an external control voltage. These results emphasize the potential of the proposed neuron and STDP learning circuits for compact and energy-efficient neuromorphic computing systems.

DC-DC buck converters are widely used in portable applications because of their high power efficiency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI filters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output filter in chaotic mode. The effectiveness of the proposed scheme was experimentally verified with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard fixed-frequency PWM reference case.

In designing ultra-efficient noise immune nanoscale circuits and systems, Schmitt triggers (STs) are vital components influencing total functionality. This article proposes an ultracompact ST using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs) and a robust ST latch. By using the unique electrical futures of the Fe-CNTFETs, the proposed ST has been designed in a particular way to only employ two transistors similar to a conventional binary inverter. Moreover, by utilizing the negative capacitance feature of the Fe-CNTFETs, the proposed ST can perform the backup and restore operation during a scheduled power gating or a sudden power outage without imposing any additional transistors, interconnects, and control signals. The proposed ST latch is hardened to soft errors occurring due to unwanted single-event upsets (SEUs). Our extensive simulations demonstrate that our proposed ST latch offers lower transistors counts (on average 34%) and more energy savings (on average 79%). On the other hand, our design has shown 5.6 times on average higher critical charge tolerance than the previous counterparts due to its soft error hardening circuity and the superior hysteresis behavior of the proposed Fe-CNTFET-based ST. Moreover, the auto-nonvolatility of the proposed ST makes the proposed latches immune to the sudden power outage, which was not devised in the previous ST latches. Our results show new pathways in designing ultracompact and efficient nonvolatile ST latches using the Fe-CNTFET technology.

The advanced neuro-computing field requires new memristor devices with great potential as synaptic emulators between pre- and postsynaptic neurons. This paper presents memristor devices with TiO₂ Nanoparticles (NPs)/Ag(Silver) and Titanium Dioxide (TiO₂) Nanoparticles (NPs)/Au(Gold) electrodes for synaptic emulators in an advanced neurocomputing application. A comparative study between Ag(Silver)- and Au(Gold)-based memristor devices is presented where the Ag electrode provides the improved performance, as compared to the Au electrode. Device characterization is observed by the Scanning Electron Microscope (SEM) image, which displays the grown electrode, while the morphology of nanoparticles (NPs) is verified by Atomic Force Microscopy (AFM). The resistive switching (RS) phenomena observed in Ag/TiO₂ and Au/TiO₂ shows the sweeping mechanism for low resistance and high resistance states. The resistive switching time of Au/TiO₂ NPs and Ag/TiO₂ NPs is calculated, while the theoretical validation of the memory window demonstrates memristor behavior as a synaptic emulator. Measurement of the capacitor–voltage curve shows that the memristor with Ag contact is a good candidate for charge storage as compared to Au. The classification of 3 × 3 pixel black/white image is demonstrated by the 3 × 3 cross bar memristor with pre- and post-neuron system. The proposed memristor devices with the Ag electrode demonstrate the adequate performance compared to the Au electrode, and may present noteworthy advantages in the field of neuromorphic computing.