Neuromorphic computing offers parallel data processing and low energy consumption and can be useful to replace conventional von Neumann computing. Memristors are two-terminal devices with varying conductance that can be used as synaptic arrays in hardware-based neuromorphic devices. In this research, we extensively investigate the analog symmetric multi-level switching characteristics of zinc tin oxide (ZTO)-based memristor devices for neuromorphic systems. A ZTO semiconductor layer is introduced between a complementary metal-oxide-semiconductor (CMOS) compatible Ni top electrode and a highly doped poly-Si bottom electrode. A variety of bio-realistic synaptic features are demonstrated, including long-term potentiation (LTP), long-term depression (LTD), and spike timing-dependent plasticity (STDP). The Ni/ZTO/Si device in which the adjustment of the number of states in conductance is realized by applying different pulse schemes is highly suitable for hardware-based neuromorphic applications. We evaluate the pattern recognition accuracy by implementing a system-level neural network simulation with ZTO-based memristor synapses. The density of states (DOS) and charge density plots reveal that oxygen vacancies in ZTO assist in generating resistive switching in the Ni/ZTO/Si device. The proposed ZTO-based memristor composed of metal-insulator-semiconductor (MIS) structure is expected to contribute to future neuromorphic applications through further studies.

In this Letter, we present reset-voltage-dependent precise tuning operation of TiO_x/Al₂O₃-based memristive devices. For the high resistance state (HRS) with high reset voltage, abrupt set operations are observed with a large variation, while the HRS obtained by low reset voltage provides gradual and uniform switching behaviors. The improvement of gradual switching and the programming accuracy are analyzed regarding cycle-to-cycle as well as device-to-device variations. We believe that these results can be applied to operate TiO_x/Al₂O₃-based memristors in areas requiring highly accurate tuning characteristics.

In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear ${C} - {V}$ characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.

We demonstrate the factors that determine the tunneling electroresistance (TER) of the ferroelectric tunnel junction (FTJ) by investigating the effects of temperature ( T ) and the number of cycles ( N ) on remnant polarization ( P_r ) and carrier transport process. The fabricated FTJs have a metal/ ferroelectric/ insulator/semiconductor structure. The P_r is increased with increasing T and N due to oxygen vacancy redistribution. However, the increased P_r in a higher T and N does not improve the TER ratio. Using current-voltage characterization and low-frequency noise spectroscopy, we reveal that the carrier transport process at the interface between the ferroelectric and dielectric layers becomes more important than P_r in determining the TER ratio.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfO _x )-based FTJ array using certain metrics. It is clear that the proposed array consisting of scaled FTJs has adequate randomness for security applications such that the array-level PUF operations are robust against model-based machine learning attacks.

We investigate the effect of post-metal annealing temperature ( ${T}_{\text {PMA}}$ ) on ferroelectric (FE) resistive switching (RS) and non-FE RS in HfOx ferroelectric tunnel junctions. Through conductance analysis and low-frequency noise spectroscopy, the effects of ${T}_{\text {PMA}}$ on RS mechanisms are demonstrated. It is revealed that the non-FE RS, redistribution of oxygen vacancies, is suppressed with an increase in ${T}_{\text {PMA}}$ . The effects of different RS mechanisms on the tunneling electroresistance and cycling endurance characteristics are systematically investigated.