Hao Zhang

Hao Zhang

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Hao Zhang

Advanced Institute of Information Technology, Peking University, Hangzhou, China

Research Focus & Metrics

Academic Career Length

6Years (2021-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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21 May 2021 in IEEE Journal of Solid-State Circuits
Verified
Journal Article
Closed access
ZWZhixuan Wang
Zhixuan Wang
HZHao Zhang
Hao Zhang
YZYihan Zhang
Yihan Zhang
LSLinxiao Shen
Linxiao Shen
JRJiayoon Ru
Jiayoon Ru
RHRu Huang
Ru Huang
This work presents an ultra-low-power software-defined always-on wake-up system to drastically decrease the system power of Internet of Things (IoTs) devices, which usually operate in random-sparse-event (RSE) scenarios. It mainly thanks to a clock-free time-shielding level-crossing ADC (TS-LCADC), software-defined clock-free multi-function detectors, and an asynchronous pipelined event-driven architecture. First, by quantifying RSE noisy signals with clock-free adaptive sampling in a signal-noise-rejecting manner, the proposed TS-LCADC reduces number of sampling points and power, and consumes only 41 nW when on-call waiting for IoT events. Second, the proposed clock-free multi-function detectors with offline and online programmability are able to character the signal features of versatile IoTs events and allow versatile and dynamic wake-up functions. Third, the proposed asynchronous pipelined event-driven architecture minimizes the system activity and thus power, because a power-hungry high-performance system (HPS) is only woken up when a detected parameter crosses its corresponding threshold. As such, the long-term average power (LTA-power) is dominated by the always-on circuits in RSE scenarios. The measurement results achieve 71–75 nW for three typical applications, i.e., heart rate, epilepsy, and keyword envelope detection. The LTA power is only 57 nW when waiting for RSE events, which is 30 $\times $ lower than a prior general-purpose wake-up chip. Compared with other works of dedicated voice and acoustic wake-up functions, this work consumes 2 $\times $ and 17 $\times $ less power, respectively, while featuring 16 $\times $ higher signal bandwidth and a broader versatility.

6 September 2023 in IEEE Journal of Solid-State Circuits
Verified
Journal Article
Closed access
HLHeyi Li
Heyi Li
KDKaixuan Du
Kaixuan Du
YBYuanxin Bao
Yuanxin Bao
YDYanchi Dong
Yanchi Dong
JRJiayoon Ru
Jiayoon Ru
RHRu Huang
Ru Huang
This article reports an energy/area-efficient zoom capacitance-to-digital converter (CDC)-based CMOS humidity sensor. It achieves the best-in-class error of $\pm$ 0.8%RH and better figure of merit (FoM $_{w}$ ; 87 fJ/c.step) than the state-of-the-art humidity sensors due to the use of the two techniques described in the following: 1) a charge-redistribution correlated level-shifting (CR-CLS) floating inverter amplifier (FIA) is proposed to increase the conventional CLS-FIA open-loop gain by at least 13.5 dB across temperature variations ( $-$ 40 $^{\circ}$ C to 85 $^{\circ}$ C) and the extreme process corners, minimizing the closed-loop FIA gain error and thus the CDC nonlinearity and humidity error and 2) a pair of stacked humidity sensors over the circuits, all of which are included in the standard CMOS process, is proposed to achieve a lower cost and decrease the area by half. The proposed CMOS humidity sensor is implemented in a 55-nm CMOS process. The measurement results show that the capacitance resolution and humidity resolution are 197 aF and 0.094%RH, respectively, at a total input capacitance of 3 pF, and the effective number of bits (ENOB) is 12.1 at a clock frequency of 2.5 MHz and a cycle number per conversion (N) of 16. The proposed humidity sensor consumes 9.57 $\mu $ W at the conversion time of 0.04 ms. The sensor exhibits a $\pm$ 0.8%RH peak-to-peak accuracy (3 $\sigma $ error of 2.5%RH) among 40 chips from 20%RH to 85%RH.

17 November 2022 in IEEE Sensors Journal
Verified
Journal Article
Closed access
HZHao Zhang
Hao Zhang
HLHeyi Li
Heyi Li
SZShichuang Zhang
Shichuang Zhang
YZYihan Zhang
Yihan Zhang
LSLinxiao Shen
Linxiao Shen
LYLe Ye
Le Ye
Ultra-high sensitivity and large-dynamic-range (DR) current-sensing front-ends (CSFE) are required in emerging biomedical applications like next-generation genesequencers (NGGSs). In this paper, an fA-level-sensitivity and 115dB-DR current-domain (CD) continuous-time (CT) Zoom ADC-based CSFE is presented. Three main techniques are proposed, including 1) A novel resistive-DAC (RDAC) with ultra-low noise and a compact area to achieve an fA-level sensitivity. 2) A CD CT SAR ADC serves as a coarse quantizer to extend the DR to be over 115dB. 3) A digital compensation scheme overcomes the offset problem of the big parasitic capacitor at the input node. Fabricated in a 180nm CMOS process, this chip only occupies an active area of 0.182mm 2 and consumes 77μW at a 2V supply voltage. At a 100Hz bandwidth (BW), it achieves the power efficiency of 389nJ per conversion and a resolution Figure-of-Merit (FoM res ) of 0.13pA 2 μJ.