Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology. Graphical Abstract

Chiplet technology has emerged as a transformative approach in integrated circuit design. Although it has attracted significant attention recently, there has been limited effort dedicated to clearly defining its concept, terminology, composition, and evolution phases etc. This survey paper gives a formal definition by proposing chiplet terminology and composition, name it as a new design methodology, then analyze over 200 recent publications from both academia and industry to establish chiplet as a technology domain composed of four distinct fields: chiplet-based SoC architecture, interconnect, EDA tools, and advanced packaging. For each field composing chiplets, the paper traces the technology development, analyze challenges, outline the evolution trend and challenges. This survey aims to provides an in-depth examination of chiplet domain and each field’s progress, offering insights drawn from literature analysis to outline the current and emerging landscape of chiplet technology.

With the rapid growth of electronic chip's performance, electric signal limits chip I/O in power consumption, reachability, and signal quality. In this letter, we propose a new chip-let architecture for chip-level optical interconnect. An optic I/O chip-let including an ultra-small optic transceiver and electronic components is implemented. Our analysis shows that the optical interconnect based on this architecture can achieve 1/3 power consumption and 1/2 area compared with traditional board-level optical interconnect in Ethernet NIC application. By adopting the architecture we proposed, the optic I/O chip-let can support any payload IC such as CPU, GPU, switch to have optic I/O.

Reconfigurable optical directed logic circuits (RODLC) aim to perform arbitrary logic operations using the optical switch network, in which the electrical signals regarded as the logic operands are applied to the optical switch to control the propagation of light over time, and the logic operation results are obtained at the output ports of the optical switch network in the form of light. In this paper, a novel RODLC is proposed and experimentally demonstrated by utilizing an optical switch array with the prosperous optical mode division multiplexing (MDM) technology to perform arbitrary logic functions. As a proof of concept, a RODLC with two optical mode (de)multiplexers and twelve thermo-optic microring resonators on a silicon-on-insulator substrate is fabricated based on standard microfabrication technology. To demonstrate its reconfigurability to perform arbitrary logic functions, eight logic operations: NOT, AND, NAND, OR, NOR, XOR, XNOR, as well as one combination operation of four-operand, with the operation speed of 10 Kbps are successfully implemented as examples. The demonstrated RODLC characterized with reconfigurability, scalability, and ability for large-scale integration, will contribute to the flourishing development of optical computing and information processing in large-scale optical hybrid integrated circuits.

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit.

Optical network-on-chip (ONoC) is a promising interconnection solution for its high bandwidth and low energy consumption. However, optical circuit-switching (OCS)-based architectures face the problem of high network congestion, low network utilization, and an overhead in power dissipation under heavy loads. In this letter, we propose an architecture called Flyover for hybrid electronic-optical network-on-chip using cluster architecture with time-division multiplex (TDM)-wavelength-division multiplex (WDM) technology. Flyover combines TDM and WDM to solve problems faced by OCS. Flyover is modularized into two network layers with cluster architecture to improve network scalability and flexibility. The state of each optical router has been configured by the control unit at the beginning of each time slot to achieve a nonblocking optical network layer. With the result of OPNET simulation, Flyover has better performance compared with equivalent OCS-mesh ONoC under various traffic patterns.