The use of technology in agriculture has been gaining significant attention recently. By employing advanced tools and automation and leveraging the latest advancements in the Internet of Things (IoT) and artificial intelligence (AI), the agricultural sector is witnessing improvements in its crop yields and overall efficiency. This paper presents the design and performance analysis of a machine learning (ML) model for agricultural applications involving acoustic sensing. This model is integrated into an efficient Artificial Intelligence of Things (AIoT) platform tailored for agriculture. The model is then used in the design of a communication network architecture and for determining the distribution of the computing load between edge devices and the cloud. The study focuses on the design, analysis, and optimization of AI deployment for reliable classification models in agricultural applications. Both the architectural level and hardware implementation are taken into consideration when designing the radio module and computing unit. Additionally, the study encompasses the design and performance analysis of the hardware used to implement the sensor node specifically developed for sound classification in agricultural applications. The novelty of this work lies in the optimization of the integrated sensor node, which combines the proposed ML model and wireless network, resulting in an agricultural-specific AIoT platform. This co-design enables significant improvements in the performance and efficiency for acoustic and ambient sensing applications.

In this article, we present a crystal-less Bluetooth low-energy (BLE) transmitter using RF reference recovery directly from GFSK-modulated BLE packets. In order to achieve fast frequency calibration from modulated signals and reduce interference from other BLE users, the transceiver consists of a back-channel wake-up receiver, a clock-recovery receiver, a transmitter, and a dual-all-digital phase-locked loop (ADPLL) frequency synthesizer for system wake-up, clock-recovery, packet transmission, and frequency calibration. An embedded averaging processing unit in the loop filter of the ADPLL is proposed to retrieve accurate frequency information from GFSK-modulated signals. A prototype chip is fabricated in 40-nm CMOS for verification. The crystal-less transmitter with clock recovery meets all BLE requirements for SIR, making this a robust solution for removing the crystal even in densely populated networks.

With the coming of age of the Internet of Things (IoT), demand on ultra-low power radios will continue to boost tremendously. Circuit imperfections, especially in power hungry blocks, i.e. the local oscillators (LO) and band pass filters (BPFs), pose a real challenge for ultra-low power (ULP) radios designers considering their tight power budget. This paper presents an investigation on the effects of circuit non-idealities on the bit-error rate (BER) performance of On-off keying (OOK) and Gaussian Frequency-shift Keying (GFSK) energy detection based wakeup radios. In particular, this paper analyzes the impact of phase noise and frequency offset in the LO, BPFs bandwidth and roll-off, noise figure (NF) on ULP receivers’ performance. The paper contributes to the ongoing research in designing ULP wireless nodes by demonstrating the tradeoffs between these non-idealities and the receiver’s sensitivity level and selectivity and show some design guidelines for energy detection (ED) based ULP radios.

This paper presents a comprehensive review of engineering techniques employed to enhance the quality factor (Q-factor) of silicon-based on-chip inductors across MHz-to-GHz frequency domains. The performance of CMOS on-chip inductors is often bottlenecked by the substrate losses, parasitic effects and resistive losses, which degrade the Q-factor. Numerous engineering techniques including substrate engineering, ground plane engineering, layout engineering and material engineering are analyzed and discussed. Substrate engineering such as substrate isolation and micromachining, ground plane engineering such as patterned ground shield and defected ground shield, layout engineering such as multilayer stacking and geometry modulation, material engineering such as magnetic core integration and conductor lamination are all investigated. A comparative evaluation of these techniques highlights the optimum approaches for attaining high-Q inductors in silicon process, mainly for CMOS compatibility.