We describe the realization of a fully-electronic label-free temperature-controlled biosensing platform aimed to overcome the Debye screening limit over a wide range of electrolyte salt concentrations. It is based on an improved version of a 90 nm CMOS integrated circuit featuring a nanocapacitor array, readout and A/D conversion circuitry, and an FPGA-based interface board with NIOS II soft processor. We describe the chip's processing, the mounting, the microfluidics, the temperature control system, as well as the calibration and compensation procedures to reduce systematic errors, which altogether make up a complete quantitative sensor platform. Capacitance spectra recorded up to 50-70 MHz are shown and successfully compared to predictions by FEM numerical simulations in the Poisson-Drift-Diffusion formalism. They demonstrate the ability of the chip to reach high upper frequency of operation, thus overcoming the low-frequency Debye screening limit at nearly physiological salt concentrations in the electrolyte, and allowing for detection of events occurring beyond the extent of the electrical double layer. Furthermore, calibrated multi-frequency measurements enable quantitative recording of capacitance spectra, whose features can reveal new properties of the analytes. The scalability of the electrode dimensions, inter-electrode pitch and size of the array make this sensing approach of quite general applicability, even in a non-bio context (e.g. gas sensing).

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( ${T}$ ), referred to as “excess 1/f noise,” observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures.

In this article, we separately investigate the role of electric field and device self-heating (SHE) in enhancing the charge emission process from Fe-related buffer traps (0.52 eV from E _c ) in AlGaN/GaN high electron mobility transistors (HEMTs). The experimental analysis was performed by means of drain current transient (DCT) measurements for either: 1) different dissipated power ( P _D,steady ) at constant drain-to-source bias ( V _DS,steady ) or 2) constant P _D,steady at different V _DS,steady 's. We found that: 1) an increase in P _D,steady yields an acceleration in the thermally activated emission process, consistently with the temperature rise induced by SHE and 2) on the other hand, the field-effect turned out to be negligible within the investigated voltage range, indicating the absence of the Poole-Frenkel effect (PFE). A qualitative analysis based on the electric field values obtained by numerical simulations is then presented to support the interpretation and conclusions.

The accurate extraction and the reliable, repeatable reduction of graphene–metal contact resistance (R_C) are still open issues in graphene technology. Here, the importance of following clear protocols when extracting R_C using the transfer length method (TLM) is demonstrated. The example of back‐gated graphene TLM structures with nickel contacts, a complementary metal oxide semiconductor compatible metal, is used here. The accurate extraction of R_C is significantly affected by generally observable Dirac voltage shifts with increasing channel lengths in ambient conditions. R_C is generally a function of the carrier density in graphene. Hence, the position of the Fermi level and the gate voltage impact the extraction of R_C. Measurements in high vacuum, on the other hand, result in dependable extraction of R_C as a function of gate voltage owing to minimal spread in Dirac voltages. The accurate measurement and extraction of important parameters like contact‐end resistance, transfer length, sheet resistance of graphene under the metal contact, and specific contact resistivity as a function of the back‐gate voltage is further assessed. The presented methodology has also been applied to devices with gold and copper contacts, with similar conclusions.

Ion-sensitive field-effect transistors (ISFETs) form a high sensitivity and scalable class of sensors, compatible with advanced complementary metal-oxide semiconductor (CMOS) processes. Despite many previous demonstrations about their merits as low-power integrated sensors, very little is known about their noise characterization when being operated in a liquid gate configuration. The noise characteristics in various regimes of their operation are important to select the most suitable conditions for signal-to-noise ratio (SNR) and power consumption. This work reports systematic DC, transient, and noise characterizations and models of a back-end of line (BEOL)-modified foundry-made ISFET used as pH sensor. The aim is to determine the sensor sensitivity and resolution to pH changes and to calibrate numerical and lumped element models, capable of supporting the interpretation of the experimental findings. The experimental sensitivity is approximately 40 mV/pH with a normalized resolution of 5 mpH per µm², in agreement with the literature state of the art. Differences in the drain current noise spectra between the ISFET and MOSFET configurations of the same device at low currents (weak inversion) suggest that the chemical noise produced by the random binding/unbinding of the H⁺ ions on the sensor surface is likely the dominant noise contribution in this regime. In contrast, at high currents (strong inversion), the two configurations provide similar drain noise levels suggesting that the noise originates in the underlying FET rather than in the sensing region.

The signal-to-noise ratio of planar ISFET pH sensors deteriorates when reducing the area occupied by the device, thus hampering the scalability of on-chip analytical systems which detect the DNA polymerase through pH measurements. Top-down nano-sized tri-gate transistors, such as silicon nanowires, are designed for high performance solid-state circuits thanks to their superior properties of voltage-to-current transduction, which can be advantageously exploited for pH sensing. A systematic study is carried out on rectangular-shaped nanowires developed in a complementary metal-oxide-semiconductor (CMOS)-compatible technology, showing that reducing the width of the devices below a few hundreds of nanometers leads to higher charge sensitivity. Moreover, devices composed of several wires in parallel further increase the exposed surface per unit footprint area, thus maximizing the signal-to-noise ratio. This technology allows a sub milli-pH unit resolution with a sensor footprint of about 1 µm², exceeding the performance of previously reported studies on silicon nanowires by two orders of magnitude.