Smart tags are compact electronic devices affixed to or embedded into objects to facilitate identification, monitoring, and data exchange. Consequently, secure authentication of these tags is a crucial issue, as objects must reliably verify their identity before sharing sensitive information with other entities. The application of Physical Unclonable Functions (PUF) as a device's “digital fingerprint” has attracted significant attention, yet existing PUF-based authentication methods exhibit security vulnerabilities, either due to the authentication protocol itself or the limited reliability of the PUF technology used. Moreover, there has been a considerable focus on the software aspect, often overlooking the critical role of hardware design, which can become a target for attacks aimed at compromising the device's identity or act as a hindrance in the manufacturing process. In light of these points, this paper introduces an identification tag architecture that leverages PUF technology, focusing on authentication. This architecture features a straightforward but efficient authentication protocol, underpinned by a new and highly stable PUF model. The overall architecture encompasses particular hardware implementation aspects that significantly simplify the tag's enrollment phase and minimize vulnerabilities to attacks. The paper also describes a prototype of this identification tag and provide detailed insights into its application.

This article introduces a novel class of static and monostable CMOS physically unclonable functions (PUFs) for hardware security applications. The PUF bitcell is based on a sub-threshold four-transistor (4T) voltage divider as the core block, along with an inverter as the output stage. The 4T voltage divider consists of two series-connected and nominally identical PMOS-only two-transistor (2T) circuits. This allows inherently random bit generation assisted by mismatch while also ensuring inherent robustness against environmental variations. A 180-nm test chip was characterized to validate our solution. Measurements of the 4T bitcell core prove its capability to generate random voltages with high dispersion (i.e., close to either ground or supply voltage levels) and high stability across a wide range of environmental conditions. The statistical PUF performance was evaluated on an $8\times32$ bitcell array without applying any post-silicon stability-enhancement technique. Raw measurements reveal a bit instability of only ~0.6% at golden key (GK) conditions (1.8 V and 25 °C), which increases up to 1.5% at 0.4 V and room temperature. When compared to prior art, our solution shows competitive performance in terms of stability, uniqueness (mean normalized inter-PUF Hamming distance (HD) of 0.493), and reproducibility (mean normalized intra-PUF HD of 0.0016), at the cost of more area-hungry design (~7200-F² bitcell area).

This paper presents a novel low-power low-voltage analog implementation of the softmax function, with electrically adjustable amplitude and slope parameters. We propose a modular design, which can be scaled by the number of inputs (and of corresponding outputs). It is composed of input current–voltage linear converter stages (1st stages), MOSFETs operating in a subthreshold regime implementing the exponential functions (2nd stages), and analog divider stages (3rd stages). Each stage is only composed of p-type MOSFET transistors. Designed in a 0.18 µm CMOS technology (TSMC), the proposed softmax circuit can be operated at a supply voltage of 500 mV. A ten-input/ten-output realization occupies a chip area of 2570 µm² and consumes only 3 µW of power, representing a very compact and energy-efficient option compared to the corresponding digital implementations.

This paper explores a class of highly stable static monostable physically unclonable functions (PUFs) based on stacked sub-threshold voltage dividers between two nominally identical sub-circuits as bitcell core block. More specifically, compared to our previous works where two-transistor (2T) and four-transistor (4T) voltage divider based PUFs were presented and analyzed, here we propose two novel topological variants based on six-transistor (6T) and eight-transistor (8T) solutions which arise from adopting a proper reverse gate-biasing strategy within the stack with the aim of improving the resilience to on-chip noise and voltage variations, while keeping the area overhead low. These novel solutions, along with those already proposed, were tested in 180-nm CMOS technology. Raw measurements show a nominal (at 1.8 V and 25 $^{\circ}$ C) bit error rate (BER) of 0.15% and 0.08% for the 6T-and 8T-based solutions, respectively, along with a BER variation of 0.016% and 0.002% per 0.1 V. With the implementation of a simple masking technique based on measurements at low supply voltage ( $V_{DD}$ $=$ 0.3 V at 25 $^{\circ}$ C) along with a temporal majority voting (TMV) scheme, a BER of 0.006% and lower than 9.77 $\times$ $10^{-5}$ %, which is the minimum observable BER for the adopted statistical set, was observed for the 6T-, and 8T-core based implementations, respectively, with a corresponding masking ratio of 8.71% and 7.59%. This is achieved with an area per bit of 5,174 $F^2$ (6T solution) and 6,994 $F^2$ (8T solution).

In this paper we present a novel Transient Effect Ring Oscillator Physical Unclonable Function for FPGAs. It exploits in an original way the carry chain resources available in modern devices. The basic cell adopted in the proposed architecture can be runtime configured to implement different oscillation paths. This property enables the possibility to output more than one bit response per cell by choosing among the configurations those that exhibit the highest reliability. Such results are achieved by adopting a specific calibration process able to identify configurations of the cells showing the highest stability and the most uncorrelated responses. When implemented on several Series 7 Xilinx devices, no unstable bits were observed at 1 V and 25 $^{\circ}$ C. Under voltage variation in the manufacturer recommended ranges, a worst case bit error rate of 0.046% is achieved. The circuit designed as here described consists of 64 cells, produces 128 response bits and consumes just 535 look-up-tables and 256 carry chains.