The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing.

X‐ray topography—a well‐known diffraction imaging method—is widely used for the characterization of extended crystal defects like dislocations. Herein, the progress toward the quantification besides the number and nature of dislocations is given. The diffracted images include additional information about tilt and strain, which can be measured in real‐time, thanks to the improved digital detection systems. This allows not only the fast mapping of huge samples like 450 mm diameter Si wafers, the in situ observation of the dislocation, or crack dynamics at high temperatures, but also the stress analysis in electronic devices in operando. In addition to typical white X‐ray beam methods like stacks of section topographs, the monochromatic diffraction laminography allows a 3D representation of the dislocation arrays. The merits and limitations of X‐ray topography are demonstrated by semiconductor materials as an example.

Basal plane dislocations (BPDs) in 4H silicon carbide (SiC) crystals grown using the physical vapor transport (PVT) method are diminishing the performance of SiC-based power electronic devices such as pn-junction diodes or MOSFETs. Therefore, understanding the generation and movement of BPDs is crucial to grow SiC suitable for device manufacturing. In this paper, the impact of the cooldown step in PVT-growth on the defect distribution is investigated utilizing two similar SiC seeds and identical growth parameters except for a cooldown duration of 40 h and 70 h, respectively. The two resulting crystals were cut into wafers, which were characterized by birefringence imaging and KOH etching. The initial defect distribution of the seed wafer was characterized by synchrotron white beam X-ray topography (SWXRT) mapping. It was found that the BPD density increases with a prolonged cooldown time. Furthermore, small angle grain boundaries based on threading edge dislocation (TED) arrays, which are normally only inherited by the seed, were also generated in the case of the crystal cooled down in 70 h. The role of temperature gradients inside the crystal during growth and post-growth concerning the generation of shear stress is discussed and supported by numerical calculations.