As a critical component of computer systems, static random access memory (SRAM) plays a significant role in the fields of high-performance computing, artificial intelligence, and the Internet of Things. However, the conventional silicon-based SRAM is facing problems such as high power consumption, integration limitations, and the need for performance improvement. For the power consumption challenge of SRAM, a novel read/write-decoupled SRAM cell is proposed in this paper. When SRAM is in a standby state, utilization of this cell can effectively reduce the leakage current, thereby reducing the static power consumption. In addition, a novel carbon–silicon heterogeneous-integrated SRAM technology is proposed in this paper. The carbon–silicon heterogeneous-integrated SRAM technology combines the high mobility, low power consumption, and low temperature process compatibility of carbon nanotubes (CNTs) with mature silicon-based fabrication processes, enabling significant optimization of access time and power consumption. The SRAM was implemented by a silicon-based 55 nm process and a carbon-based 500 nm process. The simulation results showed that when the power supply was 1.2 V, the access time of SRAM with the silicon 55 nm process was 886 ps. The static and dynamic power consumption was 91.51 nW and 1.48 mW, respectively. The SRAM with carbon–silicon heterogeneous-integrated technology achieved an access time of 872 ps, a static power consumption of 62.54 nW, and a dynamic power consumption of 1.07 mW, representing reductions of 1.58%, 31.66%, and 27.70%, respectively.

In the post-Moore era, carbon nanotube field-effect transistors (CNTFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology at and below the 5 nm node. Compact models bridge circuit design and device physics, yet the electrostatic discharge (ESD) behavior of CNTFETs remains insufficiently captured. Focusing on the local bottom-gate (LBG) CNTFET structure, which offers enhanced gate control due to its bottom-gate configuration, this paper investigates three dominant ESD-triggering mechanisms—thermionic current, tunneling leakage current, and thermal failure breakdown. Then, a hybrid compact–behavioral ESD model for CNTFETs is established. After theoretical derivation and comparison with test results, the model parameters are optimized through fitting. The simulation results exhibit excellent agreement with CNTFET measurements, particularly capturing the Human Body Model (HBM) pre-charge threshold phenomenon at 72 V and accurately predicting the subsequent voltage collapse behavior. This validates the accuracy and effectiveness of the model, laying a theoretical and experimental foundation for further construction of carbon-based standard-cell and I/O libraries.

For the application of a high-performance shortwave infrared (SWIR) detector, a fully integrated analog front-end (AFE) circuit is proposed in this paper, which includes a readout integrated circuit (ROIC) and a 12-bit/100 kHz two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC adopts a direct injection (DI) structure with a pixel size of only 10 µm × 10 µm. The column processing circuit uses a passive correlated double-sampling (CDS) circuit to reduce noise and improve dynamic range. The comparator of four inputs in the ADC solves the problem of linearity reduction caused by charge redistribution during coarse quantization. In addition, the current steering digital-to-analog converter (DAC) is used to compensate for the non-ideal characteristics of the switch, which effectively optimizes the differential nonlinearity (DNL) and integral nonlinearity (INL). The AFE is implemented using SMIC 180 nm 1P6M technology. The post-simulation results show that at a power supply voltage of 3.3 V, the AFE has a frame rate of 100 Hz and a full well capacity (FWC) of 2.8 Me⁻. The linearity can reach 99.59%, and the equivalent output noise is 243 µV. The dynamic range is 73.8 dB. Meanwhile, the signal-to-noise distortion ratio (SNDR) and effective number of bits (ENOB) are 68.38 dB and 11.06 bits, respectively.

To address the issues of insufficient responsivity and low imaging contrast of carbon-based HGFET high-sensitivity short-wave infrared (SWIR) detectors under low-light conditions, this paper proposes a high-sensitivity and high-contrast image enhancement algorithm for low-light detection, with FPGA-based hardware verification. The proposed algorithm establishes a multi-stage cooperative enhancement framework targeting key challenges such as low signal-to-noise ratio (SNR), high dark-state noise, and weak target extraction. Unlike traditional direct enhancement methods, the proposed approach first performs defective row-column correction and background noise separation based on dark-state data, which provides a clean foundation for signal reconstruction. Furthermore, an adaptive gamma correction mechanism based on image maximum value is introduced to avoid unnecessary nonlinear transformations in high-contrast regions. During the contrast enhancement stage, an exposure-constrained adaptive histogram equalization strategy is adopted to effectively suppress noise amplification and saturation in low-light scenes. Finally, an innovative dual-mode threshold selection method based on image variance is proposed, which can dynamically integrate the OTSU algorithm with statistical moment analysis to ensure robust background noise separation across both high- and low-contrast scenarios. Experimental results demonstrate that the proposed algorithm significantly improves target contrast in infrared images while preventing detail loss due to overexposure. Under microwatt-level laser power, background noise is effectively suppressed, and both imaging quality and weak target detection capability are substantially enhanced.

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems.