For the application of a high-performance shortwave infrared (SWIR) detector, a fully integrated analog front-end (AFE) circuit is proposed in this paper, which includes a readout integrated circuit (ROIC) and a 12-bit/100 kHz two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC adopts a direct injection (DI) structure with a pixel size of only 10 µm × 10 µm. The column processing circuit uses a passive correlated double-sampling (CDS) circuit to reduce noise and improve dynamic range. The comparator of four inputs in the ADC solves the problem of linearity reduction caused by charge redistribution during coarse quantization. In addition, the current steering digital-to-analog converter (DAC) is used to compensate for the non-ideal characteristics of the switch, which effectively optimizes the differential nonlinearity (DNL) and integral nonlinearity (INL). The AFE is implemented using SMIC 180 nm 1P6M technology. The post-simulation results show that at a power supply voltage of 3.3 V, the AFE has a frame rate of 100 Hz and a full well capacity (FWC) of 2.8 Me⁻. The linearity can reach 99.59%, and the equivalent output noise is 243 µV. The dynamic range is 73.8 dB. Meanwhile, the signal-to-noise distortion ratio (SNDR) and effective number of bits (ENOB) are 68.38 dB and 11.06 bits, respectively.

In the post-Moore era, carbon nanotube field-effect transistors (CNTFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology at and below the 5 nm node. Compact models bridge circuit design and device physics, yet the electrostatic discharge (ESD) behavior of CNTFETs remains insufficiently captured. Focusing on the local bottom-gate (LBG) CNTFET structure, which offers enhanced gate control due to its bottom-gate configuration, this paper investigates three dominant ESD-triggering mechanisms—thermionic current, tunneling leakage current, and thermal failure breakdown. Then, a hybrid compact–behavioral ESD model for CNTFETs is established. After theoretical derivation and comparison with test results, the model parameters are optimized through fitting. The simulation results exhibit excellent agreement with CNTFET measurements, particularly capturing the Human Body Model (HBM) pre-charge threshold phenomenon at 72 V and accurately predicting the subsequent voltage collapse behavior. This validates the accuracy and effectiveness of the model, laying a theoretical and experimental foundation for further construction of carbon-based standard-cell and I/O libraries.

As a critical component of computer systems, static random access memory (SRAM) plays a significant role in the fields of high-performance computing, artificial intelligence, and the Internet of Things. However, the conventional silicon-based SRAM is facing problems such as high power consumption, integration limitations, and the need for performance improvement. For the power consumption challenge of SRAM, a novel read/write-decoupled SRAM cell is proposed in this paper. When SRAM is in a standby state, utilization of this cell can effectively reduce the leakage current, thereby reducing the static power consumption. In addition, a novel carbon–silicon heterogeneous-integrated SRAM technology is proposed in this paper. The carbon–silicon heterogeneous-integrated SRAM technology combines the high mobility, low power consumption, and low temperature process compatibility of carbon nanotubes (CNTs) with mature silicon-based fabrication processes, enabling significant optimization of access time and power consumption. The SRAM was implemented by a silicon-based 55 nm process and a carbon-based 500 nm process. The simulation results showed that when the power supply was 1.2 V, the access time of SRAM with the silicon 55 nm process was 886 ps. The static and dynamic power consumption was 91.51 nW and 1.48 mW, respectively. The SRAM with carbon–silicon heterogeneous-integrated technology achieved an access time of 872 ps, a static power consumption of 62.54 nW, and a dynamic power consumption of 1.07 mW, representing reductions of 1.58%, 31.66%, and 27.70%, respectively.

To meet the requirements of wide-temperature reliability and fast transient response in power management ICs for automotive, aerospace, and industrial applications, this paper presents a fast-response low-dropout regulator (LDO) based on a 0.18 μm high-temperature SOI process. Benefiting from the buried oxide isolation structure of the SOI technology, leakage current and parasitic effects under high-temperature conditions are effectively suppressed. The proposed LDO employs an NMOS power transistor, with an on-chip charge pump used to enhance the gate driving capability. In addition, a triple-loop regulation scheme consisting of a main negative feedback loop, an auxiliary positive feedback loop, and a current-mode feedback loop is adopted to improve transient performance and enhance loop stability. The fabricated chip occupies an area of 2840 μm × 1490 μm and supports an input voltage range of 3–5.5 V and an output voltage range of 1.2–3.3 V. Over a temperature range of −55 °C to 175 °C, the LDO can deliver a maximum load current of 400 mA. At 175 °C, the measured overshoot and undershoot voltages are 64 mV and 94 mV, respectively, with a maximum recovery time of 336 μs. Moreover, the power supply rejection ratio (PSRR) reaches 56.8 dB at 100 Hz. Experimental results demonstrate that the proposed LDO exhibits excellent high-temperature adaptability, strong load-driving capability, and superior transient response performance.

An Analog-to-Digital Converter (ADC) is an indispensable part of image sensor systems. This paper presents a silicon-based 13-bit 100 kS/s two-step single-slope analog-to-digital converter (TS-SS ADC) for infrared image sensors with a frame rate of 100 Hz. For the charge leakage and offset voltage issues inherent in conventional TS-SS ADC, a four-terminal comparator was employed to resolve the fine ramp voltage offset caused by charge redistribution in storage and parasitic capacitors. In addition, a current-steering digital-to-analog converter (DAC) was adopted to calibrate the voltage reference of the dynamic comparator and mitigate differential nonlinearity (DNL)/integral nonlinearity (INL). To eliminate quantization dead zones, a 1-bit redundancy was incorporated into the fine quantization circuit. Finally, the quantization scheme consisted of 7-bit coarse quantization followed by 7-bit fine quantization. The ADC was implemented using an SMIC 55 nm processSemiconductor Manufacturing International Corporation, Shanghai, China. The post-simulation results show that when the power supply is 3.3 V, the ADC achieves a quantization range of 1.3 V–3 V. Operating at a 100 kS/s sampling rate, the proposed ADC exhibits an effective number of bits (ENOBs) of 11.86, a spurious-free dynamic range (SFDR) of 97.45 dB, and a signal-to-noise-and-distortion ratio (SNDR) of 73.13 dB. The power consumption of the ADC was 22.18 mW.