Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH₂F₂/CH₄/O₂/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO₂. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

This article theoretically investigates the impact of charges at the ferroelectric/interlayer interface on the depolarization field of ferroelectric FET (FeFET) with metal/ferroelectric/interlayer/Si gate structure. The interfacial charges include fixed charges and trapped/detrapped charges. We find that the positive or negative interfacial charges (~10¹³ cm⁻²) can align the directions of the depolarization field and corresponding polarization in the ferroelectric. This article may provide insight into the device design of FeFET.

In this paper, a fabrication technique of Si _0.5 Ge _0.5 Fin for the high mobility channel FinFET device is systematically investigated. Although the shallow trench isolation (STI) densification temperature is already reduced from 1050 °C to 850 °C, the Si _0.5 Ge _0.5 Fin with the STI annealing first approach still suffers from thermal instability and micro trench issue. It is no possible to further reduce the STI densification temperature using the traditional furnace annealing for the Si _0.5 Ge _0.5 Fin, because the STI densification process of 750 °C also faces the same issue with an unacceptable STI wet etching rate. Thus, a spike annealing of 1050 °C is employed to maintain Si _0.5 Ge _0.5 Fin stability and render the STI etching rate acceptable. The spike annealing treated Si _0.5 Ge _0.5 Fin maintains a better profile than the furnace annealing sample, but it still faces the micro trench issue after the STI recess. This is because the Si _0.5 Ge _0.5 Fin is already oxidized and SiGeO _x has a higher etching rate than STI oxide. Finally, a novel STI recess first process with an extra SiN capping is developed to solve both the thermal instability and the micro trench issue, and a minor Si _0.5 Ge _0.5 Fin loss with sharp Si _0.7 Ge _0.3 SRB/Si _0.5 Ge _0.5 interfaces for the STI last scheme is realized by utilizing this novel STI recess first process.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

The interface passivation of the HfO₂/Si_0.7Ge_0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al₂O₃/Si_0.7Ge_0.3 stack, the dispersive feature and interface state density (D_it) of the HfO₂/Si_0.7Ge_0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeO_x in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO₂ and cause the HfO₂/Si_0.7Ge_0.3 interface to deteriorate. Moreover, a post-HfO₂-deposition (post-O) ozone indirect oxidation is proposed for the HfO₂/Si_0.7Ge_0.3 stack; it is found that compared with pre-O sample, the D_it of the post-O sample decreases by about 50% due to less GeO_x available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO₂/Si_0.7Ge_0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the D_it of the HfO₂/Si_0.7Ge_0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO₂/Si_0.7Ge_0.3 interface with D_it of 1.53 × 10¹¹ eV⁻¹cm⁻² @ E−E_v = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO₂/IL/Si-cap/Si_0.7Ge_0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO₂/Si_0.7Ge_0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO₂ and Si_0.7Ge_0.3 substrate.