A heterojunction tunneling field effect transistor with an L-shaped gate (HJ-LTFET), which is very applicable to operate at low voltage, is proposed and studied by TCAD tools in this paper. InGaAs/GaAsSb heterojunction is applied in HJ-LTFET to enhance the ON-state current (I_ON). Owing to the quasi-broken gap energy band alignment of InGaAs/GaAsSb heterojunction, height and thickness of tunneling barrier are greatly reduced. However, the OFF-state leakage current (I_OFF) also increases significantly due to the reduced barrier height and thickness and results in an obvious source-to-drain tunneling (SDT). In order to solve this problem, an HfO2 barrier layer is inserted between source and drain. Result shows that the insertion layer can greatly suppress the horizontal tunneling leakage appears at the source and drain interface. Other optimization studies such as work function modulation, doping concentration optimization, scaling capability, and analog/RF performance analysis are carried out, too. Finally, the HJ-LTFET with a large I_ON of 213 μA/μm, a steep average SS of 8.9 mV/dec, and a suppressed I_OFF of 10⁻¹² μA/μm can be obtained. Not only that, but the fT and GBP reached the maximum values of 68.3 GHz and 7.3 GHz under the condition of Vd = 0.5 V, respectively.

Self-powered photodetectors that do not require external power support are expected to play a key role in future photodetectors due to their low power characteristics, but achieving high responsivity remains a challenge. 2D van der Waals heterojunctions are a promising technology for high-performance self-powered photodetectors due to their excellent optical and electrical properties. Here, we fabricate a self-powered photodetector based on In₂Se₃/WSe₂/ReS₂ van der Waals heterojunction self-powered photodetector. Due to the presence of ReS₂ layer, photocurrent is enhanced as a result of the increase in light absorption efficiency and the effective region for generating photogenerated carriers. The built-in electric field is enhanced by a negative ‘back-gate voltage’ along the p–n junction vertical direction generated by the electrons in the photo-generated electrons accumulation layer. Accordingly, the optical responsivity and the photoresponse speed of this heterojunction self-powered photodetector are greatly boosted. The proposed self-powered photodetector based on the In₂Se₃/WSe₂/ReS₂ heterojunction exhibits a high responsivity of 438 mA W⁻¹, which is 17 times higher compared to the In₂Se₃/WSe₂ photodetector, a self-powered current (1.1 nA) that is an order of magnitude higher than that of the In₂Se₃/WSe₂ photodetector, and a fast response time that is 250% faster. Thus the self-powered photodetector with a stronger built-in electric field and a wider depletion zone can provide a new technological support for the fabrication of high responsivity, low power consumption and high speed self-powered photodetectors based on van der Waals heterojunctions.

When semiconductor materials are exposed to radiation fields, cascade collision effects may form between the radiation particles in the radiation field and the lattice atoms in the target material, creating irradiation defects that can lead to degradation or failure of the performance of the device. In fact, 6H-SiC is one of the typical materials for third-generation broadband semiconductors and has been widely used in many areas of intense radiation, such as deep space exploration. In this paper, the irradiation cascade effect between irradiated particles of different energies in the radiation and lattice atoms in 6H-SiC target materials is simulated based on the molecular dynamics analysis method, and images of the microscopic trajectory evolution of PKA and SKA are obtained. The recombination rates of the Frenkel pairs were calculated at PKA energies of 1 keV, 2 keV, 5 keV, and 10 keV. The relationship between the number of defects, the spatial distribution pattern of defects, and the clustering of defects in the irradiation cascade effect of 6H-SiC materials with time and the energy of PKA are investigated. The results show that the clusters are dominated by vacant clusters and are mainly distributed near the trajectories of the SKA. The number and size of vacant clusters, the number of Frenkel pairs, and the intensity of cascade collisions of SKAs are positively correlated with the magnitude of the energy of the PKA. The recombination rate of Frenkel pairs is negatively correlated with the magnitude of the energy of PKA.

The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on–off function of devices. At present, most of the irradiation research on the circuit level is focused on the single event effect, and there is very little research on the total ionizing dose effect. Therefore, this study mainly analyzes the influence of TID effects on a CMOS inverter circuit based on 22 nm FDSOI transistors. First, we constructed and calibrated an N-type FDSOI metal-oxide semiconductor (NMOS) structure and P-type FDSOI metal-oxide semiconductor (PMOS) structure. The transfer characteristics and trapped charge distribution of these devices were studied under different irradiation doses. Next, we studied the TID effect on an inverter circuit composed of these two MOS transistors. The simulation results show that when the radiation dose was 400 krad (Si), the logic threshold drift of the inverter was approximately 0.052 V. These results help further investigate the impact on integrated circuits in an irradiation environment.

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

In this paper, an improved low-voltage-triggered silicon-controlled rectifier (LVTSCR) called an ultra-low-voltage-triggered SCR (ULVTSCR) is proposed and fabricated in a 40-nm CMOS process. By adding an external NMOSs-chain triggering component to the conventional LVTSCR, the proposed ULVTSCR can realize ~2 V lower trigger voltage. Meanwhile, the trigger voltage of the ULVTSCR is adjustable with the number of its incorporated NMOS transistors. Compared with the existing Diodes-chain Triggered SCR (DTSCR) scheme, the NMOSs-chain triggered ULVTSCR possesses a 25% lowered overshoot voltage in the same area consumption, and thus it is more suitable for 2.5 V circuits ESD protections considering the CDM protection applications.