A heterojunction tunneling field effect transistor with an L-shaped gate (HJ-LTFET), which is very applicable to operate at low voltage, is proposed and studied by TCAD tools in this paper. InGaAs/GaAsSb heterojunction is applied in HJ-LTFET to enhance the ON-state current (I_ON). Owing to the quasi-broken gap energy band alignment of InGaAs/GaAsSb heterojunction, height and thickness of tunneling barrier are greatly reduced. However, the OFF-state leakage current (I_OFF) also increases significantly due to the reduced barrier height and thickness and results in an obvious source-to-drain tunneling (SDT). In order to solve this problem, an HfO2 barrier layer is inserted between source and drain. Result shows that the insertion layer can greatly suppress the horizontal tunneling leakage appears at the source and drain interface. Other optimization studies such as work function modulation, doping concentration optimization, scaling capability, and analog/RF performance analysis are carried out, too. Finally, the HJ-LTFET with a large I_ON of 213 μA/μm, a steep average SS of 8.9 mV/dec, and a suppressed I_OFF of 10⁻¹² μA/μm can be obtained. Not only that, but the fT and GBP reached the maximum values of 68.3 GHz and 7.3 GHz under the condition of Vd = 0.5 V, respectively.

In this paper, an L-shaped tunneling field effect transistor (LTFET) with ferroelectric gate oxide layer (Si: HfO₂) is proposed. The electric characteristic of NC-LTFET is analyzed using Synopsys Sentaurus TCAD. Compared with the conventional LTFET, a steeper subthreshold swing (SS = 18.4 mV/dec) of NC-LTFET is obtained by the mechanism of line tunneling at low gate voltage instead of diagonal tunneling, which is caused by the non-uniform voltage across the gate oxide layer. In addition, we report the polarization gradient effect in a negative capacitance TFET for the first time. It is noted that the polarization gradient effect should not be ignored in TFET. When the polarization gradient parameter g grows larger, the dominant tunneling mechanism that affects the SS is the diagonal tunneling. The on-state current (I_on) and SS of NC-LTFET become worse.

The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on–off function of devices. At present, most of the irradiation research on the circuit level is focused on the single event effect, and there is very little research on the total ionizing dose effect. Therefore, this study mainly analyzes the influence of TID effects on a CMOS inverter circuit based on 22 nm FDSOI transistors. First, we constructed and calibrated an N-type FDSOI metal-oxide semiconductor (NMOS) structure and P-type FDSOI metal-oxide semiconductor (PMOS) structure. The transfer characteristics and trapped charge distribution of these devices were studied under different irradiation doses. Next, we studied the TID effect on an inverter circuit composed of these two MOS transistors. The simulation results show that when the radiation dose was 400 krad (Si), the logic threshold drift of the inverter was approximately 0.052 V. These results help further investigate the impact on integrated circuits in an irradiation environment.

D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the value stored in the flip-flop. On this basis, a new structure D flip-flop is proposed in this paper. This flip-flop uses an asymmetric scheme in which the master–slave latch adopts different hardening structures. By sacrificing circuit speed in exchange for stronger SEU fortification capability, the SEU threshold of this structure is improved by 10 times compared to traditional D flip-flops. It has also been compared with Dual Interlocked Storage Elements (DICEs), and it saves the area cost of six transistors compared to the DICE structure. Under the same operating conditions, the average power consumption and peak power consumption are, respectively, 9.8% and 18.8% lower than those of the DICE circuit, making it suitable for soft radiation environments where high circuit speed is not a critical requirement.

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on-off function of devices. At present, most of the irradiation research on the circuit level is focused on the single event effect, and the research on the total ionizing dose effect is very little. Therefore, this study mainly analyzes the influence of TID effects on a CMOS inverter circuit based on 22 nm FDSOI transistors. First, we constructed and calibrated an N-type FDSOI metal-oxide semiconductor (NMOS) structure and P-type FDSOI metal-oxide semiconductor (PMOS) structure. The transfer characteristics and trapped charge distribution of these devices were studied under different irradiation doses. Next, we studied the TID effect on an inverter circuit composed of these two MOS transistors. The simulation results show that when the radiation dose is 400 krad (Si), the logic threshold drift of the inverter is approximately 0.052 V. These results help further investigate the impact on integrated circuits in the irradiation environment.