When semiconductor materials are exposed to radiation fields, cascade collision effects may form between the radiation particles in the radiation field and the lattice atoms in the target material, creating irradiation defects that can lead to degradation or failure of the performance of the device. In fact, 6H-SiC is one of the typical materials for third-generation broadband semiconductors and has been widely used in many areas of intense radiation, such as deep space exploration. In this paper, the irradiation cascade effect between irradiated particles of different energies in the radiation and lattice atoms in 6H-SiC target materials is simulated based on the molecular dynamics analysis method, and images of the microscopic trajectory evolution of PKA and SKA are obtained. The recombination rates of the Frenkel pairs were calculated at PKA energies of 1 keV, 2 keV, 5 keV, and 10 keV. The relationship between the number of defects, the spatial distribution pattern of defects, and the clustering of defects in the irradiation cascade effect of 6H-SiC materials with time and the energy of PKA are investigated. The results show that the clusters are dominated by vacant clusters and are mainly distributed near the trajectories of the SKA. The number and size of vacant clusters, the number of Frenkel pairs, and the intensity of cascade collisions of SKAs are positively correlated with the magnitude of the energy of the PKA. The recombination rate of Frenkel pairs is negatively correlated with the magnitude of the energy of PKA.

In this paper, an improved low-voltage-triggered silicon-controlled rectifier (LVTSCR) called an ultra-low-voltage-triggered SCR (ULVTSCR) is proposed and fabricated in a 40-nm CMOS process. By adding an external NMOSs-chain triggering component to the conventional LVTSCR, the proposed ULVTSCR can realize ~2 V lower trigger voltage. Meanwhile, the trigger voltage of the ULVTSCR is adjustable with the number of its incorporated NMOS transistors. Compared with the existing Diodes-chain Triggered SCR (DTSCR) scheme, the NMOSs-chain triggered ULVTSCR possesses a 25% lowered overshoot voltage in the same area consumption, and thus it is more suitable for 2.5 V circuits ESD protections considering the CDM protection applications.

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

SiC devices have been typically subjected to extreme environments and complex stresses during operation, such as intense radiation and large diurnal amplitude differences on the lunar surface. Radiation displacement damage may lead to degradation or failure of the performance of semiconductor devices. In this paper, the effects of temperature and incidence angle on the irradiation cascade effect of 6H-SiC were investigated separately using the principles of molecular dynamics. Temperatures were set to 100 K, 150 K, 200 K, 250 K, 300 K, 350 K, 400 K and 450 K. The incidence direction was parallel to the specified crystal plane, with angles of 8°, 15°, 30°, 45°, 60° and 75° to the negative direction of the Z-axis. In this paper, the six types of defects were counted, and the microscopic distribution images and trajectories of each type of defect were extracted. The results show a linear relationship between the peak of the Frenkel pair and temperature. The recombination rate of Frenkel pairs depends on the local temperature and degree of aggregation at the center of the cascade collision. Increasing the angle of incidence first inhibits and then promotes the production of total defects and Frenkel pairs. The lowest number of total defects, Frenkel pairs and antisite defects are produced at a 45° incident angle. At an incidence angle of 75°, larger size hollow clusters and anti-clusters are more likely to appear in the 6H-SiC.

In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device-level simulation. The results demonstrate that, under the combined influence of these two effects, the circuit’s upset threshold and critical charge decreased by 15.4% and 23.5%, respectively. This indicates that the charge sharing effect exacerbates the single event effects. By analyzing the incident conditions of two different incident radius particles, it is concluded that the particles with a smaller incident radius have a worse impact on the SRAM circuit, and are more likely to cause the single event upset in the circuit, indicating that the ionization distribution generated by the incident particle affects the charge collection.

In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (V_t1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low V_t1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (V_h) and a low V_t1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.